Cypress CY62147DV18 manual Switching Waveforms, Read Cycle 1 Address Transition Controlled14

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CY62147DV18

MoBL2™

Switching Waveforms

Read Cycle 1 (Address Transition Controlled)[14, 15]

tRC

ADDRESS

tOHA tAA

DATA OUT

PREVIOUS DATA VALID

 

 

 

 

DATA VALID

 

 

 

Read Cycle No. 2 (OE Controlled) [15, 16]

ADDRESS

 

 

CE

 

tRC

 

 

 

 

tPD

 

t

tHZCE

OE

ACE

 

 

 

 

tDOE

tHZOE

BHE/BLE

 

tLZOE

 

 

tDBE

tHZBE

 

 

 

tLZBE

HIGH

DATA OUT

HIGH IMPEDANCE

IMPEDANCE

 

DATA VALID

 

tLZCE

 

VCC

tPU

ICC

50%

SUPPLY

50%

CURRENT

 

ISB

Notes:

14.The device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL.

15.WE is HIGH for read cycle.

16.Address valid prior to or coincident with CE and BHE, BLE transition LOW.

Document #: 38-05343 Rev. *B

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Contents Features Functional Description1Cypress Semiconductor Corporation Pin Configuration2, 3 Fbga Top ViewOperating Range Electrical Characteristics Over the Operating RangeMaximum Ratings Product PortfolioAC Test Loads and Waveforms Data Retention Characteristics Over the Operating RangeThermal Resistance BGA55 ns 70 ns Parameter Description Min Max Unit Read Cycle Switching Characteristics Over the Operating RangeData Retention Waveform Write CycleSwitching Waveforms Read Cycle 1 Address Transition Controlled14Read Cycle No OE Controlled 15 Write Cycle No WE Controlled13, 17 Write Cycle No CE Controlled13, 17Write Cycle No WE Controlled, OE LOW18 Write Cycle No BHE/BLE Controlled, OE LOWInputs/Outputs Mode Power Ordering InformationBHE BLE Package Diagram Lead Vfbga 6 x 8 x 1 mm BV48AIssue Orig. Description of Change Date Document HistoryREV ECN no