Cypress CY62147DV18 manual Pin Configuration2, 3, Fbga Top View

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Pin Configuration[2, 3, 4]

Notes:

CY62147DV18

MoBL2™

FBGA (Top View)

1

2

3

4

5

6

 

BLE

OE

A0

A1

A2

NC

A

I/O8

BHE

A3

A4

CE

I/O0

B

I/O9

I/O10

A5

A6

I/O1

I/O2

C

VSS

I/O11

A17

A7

I/O3

Vcc

D

VCC

I/O

DNU

A16

I/O

Vss

E

 

12

 

 

4

 

 

I/O14

I/O13

A14

A15

I/O5

I/O6

F

I/O

NC

A

A13

WE

I/O

G

15

 

12

 

 

7

 

NC

A8

A9

A10

A11

NC

H

2.NC pins are not internally connected on the die.

3.DNU pins have to be left floating or tied to Vss to ensure proper application.

4.Pins H1, G2, and H6 in the BGA package are address expansion pins for 8 Mb, 16 Mb, and 32 Mb, respectively.

Document #: 38-05343 Rev. *B

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Contents Cypress Semiconductor Corporation FeaturesFunctional Description1 Pin Configuration2, 3 Fbga Top ViewOperating Range Electrical Characteristics Over the Operating RangeMaximum Ratings Product PortfolioAC Test Loads and Waveforms Data Retention Characteristics Over the Operating RangeThermal Resistance BGA55 ns 70 ns Parameter Description Min Max Unit Read Cycle Switching Characteristics Over the Operating RangeData Retention Waveform Write CycleRead Cycle No OE Controlled 15 Switching WaveformsRead Cycle 1 Address Transition Controlled14 Write Cycle No WE Controlled13, 17 Write Cycle No CE Controlled13, 17Write Cycle No WE Controlled, OE LOW18 Write Cycle No BHE/BLE Controlled, OE LOWBHE BLE Inputs/Outputs Mode PowerOrdering Information Package Diagram Lead Vfbga 6 x 8 x 1 mm BV48AREV ECN no Issue Orig. Description of Change DateDocument History
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