Cypress CY62158EV30 manual Features, Logic Block Diagram Functional Description

CY62158EV30 MoBL→

8-Mbit (1024K x 8) Static RAM

Features

•Very high speed: 45 ns

—Wide voltage range: 2.20V–3.60V

•Pin compatible with CY62158DV30

•Ultra low standby power

—Typical standby current: 2 ∝A

—Maximum standby current: 8 ∝A

•Ultra low active power

—Typical active current: 1.8 mA @ f = 1 MHz

•Easy memory expansion with CE1, CE2, and OE features

•Automatic power down when deselected

•CMOS for optimum speed/power

•Offered in Pb-free 48-ball VFBGA, 44-pin TSOP II and 48-pin TSOP I packages[1]

Logic Block Diagram

Functional Description [2]

The CY62158EV30 is a high performance CMOS static RAM organized as 1024K words by 8 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL→) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption. Placing the device into standby mode reduces power consumption significantly when deselected (CE1 HIGH or CE2 LOW). The eight input and output pins (IO0 through IO7) are placed in a high impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or a write operation is in

progress (CE1 LOW and CE2 HIGH and WE LOW).

To write to the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. Data on the eight IO pins (IO0 through IO7) is then written into the location specified on the address pins (A0 through A19).

To read from the device, take Chip Enables (CE1 LOW and CE2 HIGH) and OE LOW while forcing the WE HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the IO pins. See the “Truth Table” on page 8 for a complete description of read and write modes.

	A0		DATA IN DRIVERS							IO
	A1									0
	A2									IO
	A6	DECODER		1024K x 8					AMPS	1
										IO3
	A3
	A4									IO
	A5									2
	A7	ROW		ARRAY					SENSE	IO4
	A9
	A8
	A10									IO5
	A11
CE1	A12									IO6
										IO7
CE2	WE	COLUMN DECODER							POWER
									DOWN
	OE	13	14	15	16	17	18	19
		A	A	A	A	A	A	A

Notes

1.For 48 pin TSOP I pin configuration and ordering information, please refer to CY62157EV30 Data sheet.

2.For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.

Cypress Semiconductor Corporation	• 198 Champion Court • San Jose, CA 95134-1709	•	408-943-2600
Document #: 38-05578 Rev. *D		Revised April 19, 2007

[+] Feedback