Cypress CY62158EV30 manual Pin Configurations, Product Portfolio, Ball Vfbga, Pin Tsopii, Max Typ

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CY62158EV30 MoBL

Pin Configurations [3]

48-Ball VFBGA

Top View

44-Pin TSOPII

Top View

1

2

3

4

5

6

 

NC OE

A0

A1

A2

CE2

A

NC

NC

A3

A4

CE1

NC

B

IO0

NC

A5

A6

NC

IO4

C

VSS

IO

A

A

IO

VCC

D

 

17

7

5

 

 

 

1

 

 

 

 

 

VCC

IO2

NC

A16

IO6

VSS

E

IO3

NC

A14

A15

NC

IO7

F

NC

NC

A12

A13

WE

NC

G

A18

A8

A9

A10

A11

A19

H

A4

A3

A2

A1

A0

NCCE1

NC

IO 0

IO 1

VCC

VSS

IO 2

IONC3

NC

WE

A19

A18

A17

A16

A15

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

A5

A6

A7

OE

CEA8 2

NC

NC IO 7

IO 6

VSS

VCC

IO 5

IO 4

NC

NC

A9

A10

A11

A12

A13

A14

Product Portfolio

 

 

 

 

 

 

 

 

 

Power Dissipation

 

 

 

 

VCC Range (V)

 

 

 

 

 

 

 

 

Product

 

 

Speed

 

Operating ICC (mA)

 

 

Standby, ISB2 (µA)

 

 

 

 

 

(ns)

f = 1 MHz

f = fmax

 

 

 

 

 

 

 

 

 

 

 

 

Min

 

Typ[4]

 

Max

 

Typ[4]

Max

Typ[4]

Max

 

Typ[4]

Max

CY62158EV30LL

2.2

 

3.0

 

3.6

45

1.8

3

18

25

 

2

8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes

3.NC pins are not connected on the die.

4.Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C.

Document #: 38-05578 Rev. *D

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Contents Cypress Semiconductor Corporation FeaturesLogic Block Diagram Functional Description Champion Court San Jose , CA Document # 38-05578 Rev. *DBall Vfbga Pin ConfigurationsProduct Portfolio Pin TsopiiOperating Range Electrical Characteristics Over the Operating RangeMaximum Ratings Capacitance9AC Test Loads and Waveforms Data Retention Characteristics Over the Operating RangeThermal Resistance9 Data Retention WaveformWrite Cycle Parameter Description 45 ns Unit MinRead Cycle Read Cycle No OE Controlled16 Switching WaveformsRead Cycle No Address Transition Controlled15 Write Cycle No WE Controlled14, 18 Write Cycle No CE1 or CE2 Controlled14, 18Ordering Information Inputs/Outputs Mode PowerTruth Table Write Cycle No WE Controlled, OE LOW19Package Diagrams Ball Vfbga 6 x 8 x 1 mmPin Tsop II Issue Date Orig. Description of Change Document History