CY62158EV30 MoBL→
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested.
Storage Temperature | |
Ambient Temperature with |
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Power Applied |
Supply Voltage to Ground Potential
DC Voltage Applied to Outputs |
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in | CC(max) | + 0.3V | |
DC Input Voltage[5, 6] |
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CC(max) | + 0.3V | ||
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Electrical Characteristics (Over the Operating Range)
Output Current into Outputs (LOW) | 20 mA | ||
Static Discharge Voltage |
| >2001V | |
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Latch up Current |
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| >200 mA |
Operating Range |
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Product | Range | Ambient | VCC[7] |
Temperature | |||
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CY62158EV30LL | Industrial | 2.2V – 3.6V | |
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Parameter | Description |
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| Test Conditions |
| 45 ns |
| Unit | ||
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| Min | Typ[4] | Max | ||||||
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VOH | Output HIGH Voltage |
| IOH = |
| 2.0 |
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| V | |||
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| IOH = | 2.4 |
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| V | ||||
VOL | Output LOW Voltage | IOL = 0.1 mA |
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| 0.4 | V | ||||
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| IOL = 2.1 mA, VCC > 2.70V |
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| 0.4 | V | ||||
VIH | Input HIGH Voltage |
| VCC = 2.2V to 2.7V | 1.8 |
| VCC + 0.3V | V | ||||
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| VCC = 2.7V to 3.6V | 2.2 |
| VCC + 0.3V | V | ||||
VIIL | Input LOW Voltage |
| VCC = 2.2V to 2.7V |
| 0.6 | V | |||||
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| VCC = 2.7V to 3.6V |
| 0.8 | V | |||||
IIX | Input Leakage Current | GND < VI < VCC |
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| +1 | ∝A | |||||
IOZ | Output Leakage Current | GND < VO < VCC, Output Disabled |
| +1 | ∝A | ||||||
ICC | VCC Operating Supply Current | f = fmax = 1/tRC | VCC = VCCmax |
| 18 | 25 | mA | ||||
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| IOUT = 0 mA |
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| f = 1 MHz |
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| 1.8 | 3 | mA | |||
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| CMOS levels |
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ISB1 | Automatic CE |
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| 1 > VCC – 0.2V, CE2 < 0.2V |
| 2 | 8 | ∝A | |||
| CE |
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| Power down Current — |
| VIN > VCC | – 0.2V, VIN < 0.2V) |
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| CMOS Inputs |
| f = fmax | (Address and Data Only), |
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| f = 0 (OE and WE), VCC = 3.60V |
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ISB2[8] | Automatic CE |
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| 1 > VCC – 0.2V or CE2 < 0.2V, |
| 2 | 8 | ∝A | |||
| CE |
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| Power down Current — |
| VIN > VCC | – 0.2V or VIN < 0.2V, |
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| CMOS Inputs |
| f = 0, VCC | = 3.60V |
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Capacitance[9]
Parameter | Description | Test Conditions | Max | Unit |
CIN | Input Capacitance | TA = 25°C, f = 1 MHz, | 10 | pF |
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| VCC = VCC(typ) |
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COUT | Output Capacitance | 10 | pF |
Notes
5.VIL(min) =
6.VIH(max)= VCC + 0.75V for pulse duration less than 20 ns.
7.Full device AC operation assumes a 100 ∝s ramp time from 0 to VCC(min) and 200 ∝s wait time after VCC stabilization.
8.Only chip enables (CE1 and CE2) must be at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
9.Tested initially and after any design or process changes that may affect these parameters.
Document #: | Page 3 of 11 |
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