Cypress CY62158EV30 manual Maximum Ratings, Electrical Characteristics Over the Operating Range

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CY62158EV30 MoBL

Maximum Ratings

Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested.

Storage Temperature

–65°C to +150°C

Ambient Temperature with

 

Power Applied

–55°C to +125°C

Supply Voltage to Ground Potential –0.3V to VCC(max) + 0.3V

DC Voltage Applied to Outputs

 

 

 

in High-Z State[5, 6]

–0.3V to V

CC(max)

+ 0.3V

DC Input Voltage[5, 6]

 

 

–0.3V to V

CC(max)

+ 0.3V

 

 

 

Electrical Characteristics (Over the Operating Range)

Output Current into Outputs (LOW)

20 mA

Static Discharge Voltage

 

>2001V

(MIL-STD-883, Method 3015)

 

 

Latch up Current

 

 

>200 mA

Operating Range

 

 

 

 

 

 

Product

Range

Ambient

VCC[7]

Temperature

 

 

(TA)

 

CY62158EV30LL

Industrial

–40°C to +85°C

2.2V – 3.6V

 

 

 

 

Parameter

Description

 

 

 

Test Conditions

 

45 ns

 

Unit

 

 

 

 

 

 

 

 

 

Min

Typ[4]

Max

 

 

 

 

 

 

 

 

 

VOH

Output HIGH Voltage

 

IOH = –0.1 mA

 

2.0

 

 

V

 

 

 

IOH = –1.0 mA, VCC > 2.70V

2.4

 

 

V

VOL

Output LOW Voltage

IOL = 0.1 mA

 

 

 

0.4

V

 

 

 

IOL = 2.1 mA, VCC > 2.70V

 

 

0.4

V

VIH

Input HIGH Voltage

 

VCC = 2.2V to 2.7V

1.8

 

VCC + 0.3V

V

 

 

 

VCC = 2.7V to 3.6V

2.2

 

VCC + 0.3V

V

VIIL

Input LOW Voltage

 

VCC = 2.2V to 2.7V

–0.3

 

0.6

V

 

 

 

VCC = 2.7V to 3.6V

–0.3

 

0.8

V

IIX

Input Leakage Current

GND < VI < VCC

 

–1

 

+1

A

IOZ

Output Leakage Current

GND < VO < VCC, Output Disabled

–1

 

+1

A

ICC

VCC Operating Supply Current

f = fmax = 1/tRC

VCC = VCCmax

 

18

25

mA

 

 

 

 

 

IOUT = 0 mA

 

 

 

 

 

 

 

f = 1 MHz

 

 

1.8

3

mA

 

 

 

 

 

 

 

CMOS levels

 

 

 

 

ISB1

Automatic CE

 

 

1 > VCC – 0.2V, CE2 < 0.2V

 

2

8

A

 

CE

 

 

Power down Current —

 

VIN > VCC

– 0.2V, VIN < 0.2V)

 

 

 

 

 

CMOS Inputs

 

f = fmax

(Address and Data Only),

 

 

 

 

 

 

f = 0 (OE and WE), VCC = 3.60V

 

 

 

 

 

 

 

 

 

 

 

ISB2[8]

Automatic CE

 

 

1 > VCC – 0.2V or CE2 < 0.2V,

 

2

8

A

 

CE

 

 

Power down Current —

 

VIN > VCC

– 0.2V or VIN < 0.2V,

 

 

 

 

 

CMOS Inputs

 

f = 0, VCC

= 3.60V

 

 

 

 

Capacitance[9]

Parameter

Description

Test Conditions

Max

Unit

CIN

Input Capacitance

TA = 25°C, f = 1 MHz,

10

pF

 

 

VCC = VCC(typ)

 

 

COUT

Output Capacitance

10

pF

Notes

5.VIL(min) = –2.0V for pulse durations less than 20 ns.

6.VIH(max)= VCC + 0.75V for pulse duration less than 20 ns.

7.Full device AC operation assumes a 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization.

8.Only chip enables (CE1 and CE2) must be at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating.

9.Tested initially and after any design or process changes that may affect these parameters.

Document #: 38-05578 Rev. *D

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Contents Champion Court San Jose , CA Document # 38-05578 Rev. *D FeaturesLogic Block Diagram Functional Description Cypress Semiconductor CorporationPin Tsopii Pin ConfigurationsProduct Portfolio Ball VfbgaCapacitance9 Electrical Characteristics Over the Operating RangeMaximum Ratings Operating RangeData Retention Waveform Data Retention Characteristics Over the Operating RangeThermal Resistance9 AC Test Loads and WaveformsParameter Description 45 ns Unit Min Read CycleWrite Cycle Switching Waveforms Read Cycle No Address Transition Controlled15Read Cycle No OE Controlled16 Write Cycle No CE1 or CE2 Controlled14, 18 Write Cycle No WE Controlled14, 18Write Cycle No WE Controlled, OE LOW19 Inputs/Outputs Mode PowerTruth Table Ordering InformationBall Vfbga 6 x 8 x 1 mm Package DiagramsPin Tsop II Document History Issue Date Orig. Description of Change