Cypress CY62158EV30 manual Switching Waveforms, Read Cycle No Address Transition Controlled15

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CY62158EV30 MoBL

Switching Waveforms

Read Cycle No. 1 (Address Transition Controlled)[15, 16]

ADDRESS

tOHA

tRC

tAA

DATA OUT

PREVIOUS DATA VALID

Read Cycle No. 2 (OE Controlled)[16, 17]

DATA VALID

ADDRESS

 

 

 

 

CE1

 

tRC

 

 

 

 

 

 

CE2

 

 

 

 

 

tACE

 

 

 

OE

 

 

 

 

 

tDOE

tHZOE

 

 

 

tHZCE

 

 

 

tLZOE

HIGH

 

DATA OUT

HIGH IMPEDANCE

DATA VALID

IMPEDANCE

 

 

 

 

 

 

 

VCC

tLZCE

tPD

 

 

t

I

CC

SUPPLY

PU

 

50%

50%

 

 

CURRENT

 

 

ISB

Notes

15.Device is continuously selected. OE, CE1 = VIL, CE2 = VIH.

16.WE is HIGH for read cycle.

17.Address valid before or similar to CE1 transition LOW and CE2 transition HIGH.

Document #: 38-05578 Rev. *D

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Contents Cypress Semiconductor Corporation FeaturesLogic Block Diagram Functional Description Champion Court San Jose , CA Document # 38-05578 Rev. *DBall Vfbga Pin ConfigurationsProduct Portfolio Pin TsopiiOperating Range Electrical Characteristics Over the Operating RangeMaximum Ratings Capacitance9AC Test Loads and Waveforms Data Retention Characteristics Over the Operating RangeThermal Resistance9 Data Retention WaveformParameter Description 45 ns Unit Min Read CycleWrite Cycle Switching Waveforms Read Cycle No Address Transition Controlled15Read Cycle No OE Controlled16 Write Cycle No WE Controlled14, 18 Write Cycle No CE1 or CE2 Controlled14, 18Ordering Information Inputs/Outputs Mode PowerTruth Table Write Cycle No WE Controlled, OE LOW19Package Diagrams Ball Vfbga 6 x 8 x 1 mmPin Tsop II Issue Date Orig. Description of Change Document History