CY14B256K
Document Title: CY14B256K 256 Kbit (32K x 8) nvSRAM with Real Time Clock
Document Number:
Rev. | ECN | Orig. of Change | Submission | Description of Change | |||
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*H | 2663934 | GVCH/PYRS | 02/24/09 | Updated Features section | |||
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| Updated pin definition of | WE | pin | |
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| Updated “Reading the clock”, “Backup Power”, “Stopping and | |||
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| starting the Oscillator” and “Alarm” descriptions under RTC | |||
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| operation | |||
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| Modified “Figure 4. RTC Recommended Component Configuration” | |||
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| Added footnote 4 | |||
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| Added footnote 6 | |||
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| Added default values to RTC Register Map” table | |||
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| Updated flag register description in Register Map Detail” table | |||
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| Added Industrial specs for 25ns and 35ns speed | |||
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| Changed VIH from vcc+0.3 to Vcc+0.5 | |||
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| Added “Data Retention and Endurance” table on page 15 | |||
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| Added thermal resistance values | |||
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| Added alternate parameters in the AC switching characteristics | |||
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| table | |||
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| Renamed tOH to tOHA | |||
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| Changed tHRECALL from 20 to 40ms | |||
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| Changed tRECALL spec from 100μs to 170μs (Including tss of 70us) | |||
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| Renamed tAS to tSA | |||
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| Renamed tGHAX to tHA | |||
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| Renamed tHLHX to tPHSB | |||
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| Updated Figure 16 | |||
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| Added truth table for SRAM operations | |||
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Document Number: | Page 27 of 28 |
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