Cypress CY14B256K manual Parameter Cypress Alt

Page 18

CY14B256K

AC Switching Characteristics (continued)

Parameter

Cypress

Alt.

Parameter

Parameter

 

 

Description

25 ns

35 ns

45 ns

Min

Max

Min

Max

Min

Max

 

 

 

 

 

 

Unit

SRAM Write Cycle

tWC

tAVAV

Write Cycle Time

25

 

35

 

45

 

ns

tPWE

tWLWH, tWLEH

Write Pulse Width

20

 

25

 

30

 

ns

tSCE

tELWH, tELEH

Chip Enable To End of Write

20

 

25

 

30

 

ns

tSD

tDVWH, tDVEH

Data Setup to End of Write

10

 

12

 

15

 

ns

tHD

tWHDX, tEHDX

Data Hold After End of Write

0

 

0

 

0

 

ns

tAW

tAVWH, tAVEH

Address Setup to End of Write

20

 

25

 

30

 

ns

tSA

tAVWL, tAVEL

Address Setup to Start of Write

0

 

0

 

0

 

ns

tHA

tWHAX, tEHAX

Address Hold After End of Write

0

 

0

 

0

 

ns

tHZWE [12, 15]

tWLQZ

Write Enable to Output Disable

 

10

 

13

 

15

ns

tLZWE [12]

tWHQX

Output Active After End of Write

3

 

3

 

3

 

ns

Figure 10. SRAM Write Cycle 1: WE Controlled [14, 16]

 

tWC

ADDRESS

 

 

tSCE

CE

 

 

tAW

 

tSA

WE

tPWE

 

 

tSD

DATA IN

DATA VALID

 

tHZWE

 

HIGH IMPEDANCE

DATA OUT

PREVIOUS DATA

tHA

tHD

tLZWE

Figure 11. SRAM Write Cycle 2: CE Controlled

ADDRESS

CE

WE

DATA IN

DATA OUT

tSA

tWC

tSCE

 

 

 

tHA

 

 

tAW

tPWE

tSD tHD

DATA VALID

HIGH IMPEDANCE

Notes

15.If WE is Low when CE goes Low, the outputs remain in the High Impedance State.

16.CE or WE are greater than VIH during address transitions.

Document Number: 001-06431 Rev. *H

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Contents Functional Description FeaturesLogic Block Diagram Cypress Semiconductor Corporation 198 Champion CourtPin Configurations Pin DefinitionsDevice Operation AutoStore OperationHardware Store HSB Operation Software Recall Hardware Recall Power UpSoftware Store Data ProtectionLow Average Active Power Best Practices Current versus Cycle TimeMode Selection A13-A0 Power Real Time Clock Operation Alarm Watchdog TimerCalibrating the Clock Interrupt Register Power MonitorInterrupts Flags RegisterInterrupt Block Diagram RTC Register Map5 BCD Format Data Function/Range WDF OscfDate Time Keeping Hours 0x7FFB Register Map Detail Time Keeping Years 0x7FFF 10s YearsTime Keeping Months 0x7FFE 10s Month Time Keeping Minutes 0x7FFA0x7FF7 Alarm Day 0x7FF5Register Map Detail Calibration/Control 0X7FF8 Interrupt Status/Control 0x7FF6Alarm Seconds 0x7FF2 Register Map Detail Alarm Hours 0x7FF4 10s Alarm HoursTo ignore the hours value Alarm Minutes 0x7FF3 When the Flags register is read or on power-upOperating Range DC Electrical CharacteristicsMaximum Ratings RangeThermal Resistance Data Retention and EnduranceCapacitance AC Test ConditionsAC Switching Characteristics Parameter Sram Read CycleParameter Cypress Alt Description 25 ns 35 ns 45 ns Min Max Unit Sram Write CycleAutoStore or Power Up Recall Parameter Description CY14B256K Unit Min MaxSoftware Controlled STORE/RECALL Cycles 20 Parameter Alt Description 25 ns 35 ns 45 ns Unit Min MaxSoft Sequence Commands Hardware Store CycleRTC Characteristics Inputs and Outputs Mode PowerTruth Table For Sram Operations Part Numbering Nomenclature CY 14 B 256 K SP 25 X C T Ordering Information Package Diagrams Pin Shrunk Small Outline PackageDocument History Orig. of Change Submission Description of Change DateStarting the Oscillator and Alarm descriptions under RTC Updated Features sectionUpdated Reading the clock, Backup Power, Stopping Added default values to RTC Register Map tableSales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsUSB