Cypress CY14B101L manual Hardware Mode Selection A15 A0 Power

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CY14B101L

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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Table 1. Hardware Mode Selection

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A15 – A0

Mode

IO

Power

 

 

 

CE

WE

OE

 

 

 

H

 

X

 

X

 

X

Not Selected

Output High Z

Standby

 

 

 

L

 

H

 

L

 

X

Read SRAM

Output Data

Active[3]

 

 

 

L

 

L

 

X

 

X

Write SRAM

Input Data

Active

 

 

 

L

 

H

 

L

 

0x4E38

Read SRAM

Output Data

Active[1, 2, 3]

 

 

 

 

 

 

 

 

 

 

 

 

0xB1C7

Read SRAM

Output Data

 

 

 

 

 

 

 

 

 

 

 

 

 

0x83E0

Read SRAM

Output Data

 

 

 

 

 

 

 

 

 

 

 

 

 

0x7C1F

Read SRAM

Output Data

 

 

 

 

 

 

 

 

 

 

 

 

 

0x703F

Read SRAM

Output Data

 

 

 

 

 

 

 

 

 

 

 

 

 

0x8B45

AutoStore Disable

Output Data

 

 

 

 

L

 

H

 

L

 

0x4E38

Read SRAM

Output Data

Active[1, 2, 3]

 

 

 

 

 

 

 

 

 

 

 

 

0xB1C7

Read SRAM

Output Data

 

 

 

 

 

 

 

 

 

 

 

 

 

0x83E0

Read SRAM

Output Data

 

 

 

 

 

 

 

 

 

 

 

 

 

0x7C1F

Read SRAM

Output Data

 

 

 

 

 

 

 

 

 

 

 

 

 

0x703F

Read SRAM

Output Data

 

 

 

 

 

 

 

 

 

 

 

 

 

0x4B46

AutoStore Enable

Output Data

 

 

 

 

L

 

H

 

L

 

0x4E38

Read SRAM

Output Data

Active ICC2[1, 2, 3]

 

 

 

 

 

 

 

 

 

 

 

 

0xB1C7

Read SRAM

Output Data

 

 

 

 

 

 

 

 

 

 

 

 

 

0x83E0

Read SRAM

Output Data

 

 

 

 

 

 

 

 

 

 

 

 

 

0x7C1F

Read SRAM

Output Data

 

 

 

 

 

 

 

 

 

 

 

 

 

0x703F

Read SRAM

Output Data

 

 

 

 

 

 

 

 

 

 

 

 

 

0x8FC0

Nonvolatile Store

Output High Z

 

 

 

 

L

 

H

 

L

 

0x4E38

Read SRAM

Output Data

Active[1, 2, 3]

 

 

 

 

 

 

 

 

 

 

 

 

0xB1C7

Read SRAM

Output Data

 

 

 

 

 

 

 

 

 

 

 

 

 

0x83E0

Read SRAM

Output Data

 

 

 

 

 

 

 

 

 

 

 

 

 

0x7C1F

Read SRAM

Output Data

 

 

 

 

 

 

 

 

 

 

 

 

 

0x703F

Read SRAM

Output Data

 

 

 

 

 

 

 

 

 

 

 

 

 

0x4C63

Nonvolatile Recall

Output High Z

 

 

 

Notes

1.The six consecutive address locations are in the order listed. WE is HIGH during all six cycles to enable a nonvolatile cycle.

2.While there are 17 address lines on the CY14B101L, only the lower 16 lines are used to control software modes.

3.IO state depends on the state of OE. The IO table shown is based on OE Low.

Document Number: 001-06400 Rev. *I

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Contents Functional Description FeaturesLogic Block Diagram Cypress Semiconductor CorporationPinouts Pin DefinitionsSram Write Device OperationSram Read AutoStore OperationSoftware Store Hardware Recall Power UpLow Average Active Power Software RecallPreventing Store Best PracticesHardware Mode Selection A15 A0 Power Maximum Ratings DC Electrical CharacteristicsRange Ambient Temperature Operating RangeThermal Resistance Data Retention and EnduranceCapacitance AC Test ConditionsMin Max AC Switching CharacteristicsSwitching Waveforms ParameterAddress Setup to End of Write Chip Enable To End of WriteData Setup to End of Write Address Setup to Start of WriteAutoStore or Power Up Recall Parameter Alt Description CY14B101L Unit Min MaxSoftware Controlled STORE/RECALL Cycle Parameter Alt Description 25 ns 35 ns 45 ns Unit Min MaxHardware Store Cycle Parameter Alt Description CY14B101L Unit MinHardware Store Pulse Width Part Numbering Nomenclature CY 14 B 101 L SZ 25 X C T Ordering InformationPackage Diagrams Speed Ordering CodePackage Type Operating Range Pin Shrunk Small Outline Package Document History Document Title CY14B101L 1 Mbit 128K x 8 nvSRAMSales, Solutions, and Legal Information USB