Cypress CY14B101L manual Write Cycle Time, Write Pulse Width, Chip Enable To End of Write

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CY14B101L

 

 

 

 

 

 

 

 

 

 

 

SRAM Write Cycle

 

 

 

 

 

 

 

 

 

 

Parameter

 

Description

25 ns

35 ns

45 ns

Unit

Cypress

 

Alt

 

Min

Max

Min

Max

Min

Max

Parameter

 

 

 

 

 

 

 

 

 

 

 

 

 

tWC

 

tAVAV

 

Write Cycle Time

25

 

35

 

45

 

ns

tPWE

 

tWLWH, tWLEH

 

Write Pulse Width

20

 

25

 

30

 

ns

tSCE

 

tELWH, tELEH

 

Chip Enable To End of Write

20

 

25

 

30

 

ns

tSD

 

tDVWH, tDVEH

 

Data Setup to End of Write

10

 

12

 

15

 

ns

tHD

 

tWHDX, tEHDX

 

Data Hold After End of Write

0

 

0

 

0

 

ns

tAW

 

tAVWH, tAVEH

 

Address Setup to End of Write

20

 

25

 

30

 

ns

tSA

 

tAVWL, tAVEL

 

Address Setup to Start of Write

0

 

0

 

0

 

ns

tHA

 

tWHAX, tEHAX

 

Address Hold After End of Write

0

 

0

 

0

 

ns

tHZWE [9,11]

 

tWLQZ

 

Write Enable to Output Disable

 

10

 

13

 

15

ns

tLZWE [9]

 

tWHQX

 

Output Active After End of Write

3

 

3

 

3

 

ns

Switching Waveforms

Figure 7. SRAM Write Cycle 1: WE Controlled [11, 12]

 

tWC

ADDRESS

 

 

tSCE

CE

 

 

tAW

 

tSA

WE

tPWE

 

 

tSD

DATA IN

DATA VALID

 

tHZWE

 

HIGH IMPEDANCE

DATA OUT

PREVIOUS DATA

tHA

tHD

tLZWE

Figure 8. SRAM Write Cycle 2: CE and OE Controlled [11, 12]

ADDRESS

CE

WE

DATA IN

DATA OUT

tWC

tSA

 

 

 

tSCE

 

 

 

tHA

 

 

 

 

 

 

 

 

 

 

 

 

 

tAW

tPWE

tSD tHD

DATA VALID

HIGH IMPEDANCE

Notes

11.If WE is Low when CE goes Low, the outputs remain in the high impedance state.

12.CE or WE must be greater than VIH during address transitions.

Document Number: 001-06400 Rev. *I

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Contents Functional Description FeaturesLogic Block Diagram Cypress Semiconductor CorporationPinouts Pin DefinitionsSram Write Device OperationSram Read AutoStore OperationSoftware Store Hardware Recall Power UpLow Average Active Power Software RecallPreventing Store Best PracticesHardware Mode Selection A15 A0 Power Maximum Ratings DC Electrical CharacteristicsRange Ambient Temperature Operating RangeThermal Resistance Data Retention and EnduranceCapacitance AC Test ConditionsMin Max AC Switching CharacteristicsSwitching Waveforms ParameterAddress Setup to End of Write Chip Enable To End of WriteData Setup to End of Write Address Setup to Start of WriteAutoStore or Power Up Recall Parameter Alt Description CY14B101L Unit Min MaxSoftware Controlled STORE/RECALL Cycle Parameter Alt Description 25 ns 35 ns 45 ns Unit Min MaxParameter Alt Description CY14B101L Unit Min Hardware Store CycleHardware Store Pulse Width Part Numbering Nomenclature CY 14 B 101 L SZ 25 X C T Ordering InformationSpeed Ordering Code Package DiagramsPackage Type Operating Range Pin Shrunk Small Outline Package Document History Document Title CY14B101L 1 Mbit 128K x 8 nvSRAMSales, Solutions, and Legal Information USB