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| PRELIMINARY | CY14B101P | |||
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Document History Page |
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Document Title: CY14B101P 1 Mbit (128K x 8) Serial SPI nvSRAM with Real Time Clock |
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REV. | ECN NO. | Submission | Orig. of | Description of Change |
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Date | Change |
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** | 1939467 | See ECN | UNC/AESA | New Data Sheet |
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*A | 2607447 | 11/21/2008 | GSIN/ | Updated the “Feature” section, Clock rate changed from 40 MHz to 25 MHz |
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| GVCH/AESA | Updated nvSRAM STORE, RECALL, AutoStore Enable/Disable sections |
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| AutoStore Enable and Disable, Updated SPI with following changes: |
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| nvSRAM special instructions |
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| Added READ RTC and WRITE RTC instructions. |
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| Changed RTC recommended configuration values. |
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| Updated tOCS values for normal and room temperature |
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| Other changes as per new EROS |
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| Changed title to “CY14B101PA 1Mbit (128K x 8) Serial SPI nvSRAM with |
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*B | 2654487 | 02/04/2009 | GVCH/GSIN/ | Moved from Advance information to Preliminary |
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| PYRS | Changed part number from CY14B101PA to CY14B101P |
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| Changed X1, X2 pin names to Xout, Xin respectively |
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| Updated pin description of VCAP pin |
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| Updated Device operation and SPI peripheral interface description |
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| Added Factory setting values for BP1, BP2 and WPEN bits |
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| Updated Real Time Clock operation description |
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| Added footnote 2 |
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| Added default values to RTC Register Map” table 8 |
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| Added footnote 3 |
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| Updated flag register description in Register Map Detail” table 9 |
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| Changed C1, C2 values to 21pF, 21pF respectively |
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| Changed ICC2 from 5 mA to 10 mA |
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| Changed IBAK value from 350 nA to 450 nA at hot temperature |
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| Changed VRTCcap typical value from 2.4V to 3.0V |
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Document #: | Page 31 of 32 |
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