Cypress CY14B101P manual SPI Modes, System Configuration Using SPI nvSRAM

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PRELIMINARYCY14B101P

Figure 3. System Configuration Using SPI nvSRAM

S C K
M O S I
M IS O
S C K	S I	S O	S C K	S I	S O
u C o n tro lle r
C Y 1 4B 10 1 P			C Y 1 4 B 1 0 1P
C S		H O L D	C S		H O L D
C S 1
H O L D 1
C S 2
H O L D 2

SPI Modes

CY14B101P device may be driven by a microcontroller with its SPI peripheral running in either of the following two modes:

■SPI Mode 0 (CPOL=0, CPHA=0)

■SPI Mode 3 (CPOL=1, CPHA=1)

For both these modes, input data is latched in on the rising edge of Serial Clock (SCK) starting from the first rising edge after CS goes active. If the clock starts from a HIGH state (in mode 3), the first rising edge after the clock toggles are considered. The output data is available on the falling edge of Serial Clock (SCK).

Figure 4. SPI Mode 0

CS
	0	1	2	3	4	5		6	7
SCK
SI	7	6	5	4	3	2	1		0

MSBLSB

The two SPI modes are shown in Figure 4 and Figure 5. The status of clock when the bus master is in Standby mode and not transferring data is:

■SCK remains at 0 for Mode 0

■SCK remains at 1 for Mode 3

CPOL and CPHA bits must be set in the SPI controller for the either Mode 0 or Mode 3. CY14B101P detects the SPI mode from the status of SCK pin when device is selected by bringing the CS pin LOW. If SCK pin is LOW when device is selected, SPI Mode 0 is assumed and if SCK pin is HIGH, CY14B101P works in SPI Mode 3.

Figure 5. SPI Mode 3

CS

0 1 2 3 4 5 6 7

SCK

SI

7

6

5

4

3

2

1

0

MSBLSB

Document #: 001-44109 Rev. *B

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Contents Overview FeaturesLogic Block Diagram Sram ArrayPinouts Pin Definitions Pin Name Type DescriptionHold Sram Read Device OperationSram Write Store OperationSerial Peripheral Interface Commonly used terms used in SPI protocol are given below SPI MasterSystem Configuration Using SPI nvSRAM SPI ModesSPI Operating Features SPI Functional DescriptionStatus Register Read Status Register Rdsr InstructionWrite Status Register Wrsr Instruction Write Protection and Block Protection Write Enable Wren InstructionWrite Disable Wrdi Instruction Block ProtectionWrite Sequence Write Memory AccessRead Sequence Read Wpen WENBurst Mode Read Instruction Timing Read RTC Rdrtc InstructionWrite RTC Wrtc Instruction AutoStore DisableNvSRAM Special Instructions Software Store StoreSoftware Recall Recall AutoStore Disable AsdisbAutoStore Enable Asenb Hold Pin OperationReal Time Clock Operation Alarm Watchdog TimerCalibrating the Clock Interrupts Power MonitorInterrupt Register Flags RegisterAccessing the Real Time Clock through SPI RTC Recommended Component ConfigurationRTC Register Map1 BCD Format Data Function/Range WDF OscfOscen Alarm Minutes Alarm DayAlarm Hours Register Map DetailFlags 0x00 Register Map Detail Alarm SecondsTime Keeping Centuries WDF Oscf CALOperating Range DC Electrical CharacteristicsMaximum Ratings Parameter Description Test Conditions Min Max UnitThermal Resistance Data Retention and EnduranceCapacitance AC Test ConditionsAC Switching Characteristics ~ ~ ~ ~ AutoStore or Power Up Recall Switching WaveformsParameters Description CY14B101P Unit Min Max CY14B101P Parameter Description To Output Active Time when write latch not setHardware Store Cycle Hardware Store Pulse WidthPart Numbering Nomenclature Ordering Code Package Diagram Package Type Operating RangeOrdering Information CY 14 B 101 P SF X C TPackage Diagrams Pin 300 mil Soic PackageDocument History REV ECN noSubmission Orig. Description of Change Date Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsUSB