CY62148E MoBL®
4-Mbit (512K x 8) Static RAM
Features
•Very high speed: 45 ns
•Voltage range:
•Pin compatible with CY62148B
•Ultra low standby power
—Typical standby current: 1 µA
—Maximum standby current: 7 µA (Industrial)
•Ultra low active power
—Typical active current: 2.0 mA @ f = 1 MHz
•Easy memory expansion with CE, and OE features
•Automatic power down when deselected
•CMOS for optimum speed and power
•Available in
Product Portfolio
Functional Description [1]
The CY62148E is a high performance CMOS static RAM organized as 512K words by 8 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL→) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. Placing the device into standby mode reduces power consumption by more than 99% when deselected (CE HIGH). The eight input and output pins (IO0 through IO7) are placed in a high impedance state when:
•Deselected (CE HIGH)
•Outputs are disabled (OE HIGH)
•Write operation is active (CE LOW and WE LOW)
To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight IO pins (IO0 through IO7) is then written into the location specified on the address pins (A0 through A18).
To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the IO pins.
|
|
|
|
|
|
|
|
| Power Dissipation |
| ||
|
|
|
|
|
| Speed |
|
|
|
|
|
|
Product | Range | VCC Range (V) | Operating ICC (mA) |
|
| |||||||
(ns) | Standby ISB2 (∝A) | |||||||||||
|
|
|
|
|
|
| f = 1MHz | f = fmax | ||||
|
|
|
|
|
|
|
|
| ||||
|
|
| Min | Typ [3] | Max |
| Typ [3] | Max | Typ [3] | Max | Typ [3] | Max |
CY62148ELL | TSOP II | Ind’l | 4.5 | 5.0 | 5.5 | 45 | 2 | 2.5 | 15 | 20 | 1 | 7 |
|
|
|
|
|
|
|
|
|
|
|
|
|
CY62148ELL | SOIC |
| 4.5 | 5.0 | 5.5 | 55 | 2 | 2.5 | 15 | 20 | 1 | 7 |
|
|
|
|
|
|
|
|
|
|
|
|
|
Notes
1.For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.
2.SOIC package is available only in 55 ns speed bin.
3.Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C.
Cypress Semiconductor Corporation | • | 198 Champion Court • San Jose, CA | • | |
Document #: |
| Revised March 28, 2007 | ||
[+] Feedback