Cypress CY62148E manual Switching Waveforms, Read Cycle No Address Transition Controlled 16

Page 6

CY62148E MoBL®

Switching Waveforms

Read Cycle No. 1 (Address Transition Controlled) [16, 17]

tRC

ADDRESS

tAA

tOHA

DATA OUT

PREVIOUS DATA VALID

Read Cycle No. 2 (OE Controlled) [17, 18]

DATA VALID

ADDRESS
		tRC
CE
	tACE
OE		tHZOE
	tDOE	tHZOE
	tDOE	tHZCE
	tLZOE	tHZCE	HIGH
DATA OUT	HIGH IMPEDANCE	DATA VALID	IMPEDANCE
		DATA VALID
	tLZCE
	tLZCE	tPD
V	tPU	tPD	ICC
CC	50%		50%
SUPPLY	50%		50%
CURRENT			ISB

Write Cycle No. 1 (WE Controlled, OE HIGH During Write) [19, 20]

		tWC
ADDRESS
		tSCE
CE
	tAW		tHA
	tSA	tPWE
WE
OE
		tSD	t
			HD
DATA IO	NOTE 21	DATA VALID
	tHZOE

Notes:

16.Device is continuously selected. OE, CE = VIL.

17.WE is HIGH for read cycles.

18.Address valid before or similar to CE transition LOW.

19.Data IO is high impedance if OE = VIH.

20.If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state.

21.During this period, the IOs are in output state and input signals must not be applied.

Document #: 38-05442 Rev. *F

Page 6 of 10

[+] Feedback

Image 6

Contents Tsop FeaturesProduct Portfolio Functional Description SoicLogic Block Diagram Pin Configuration 2Pin SOIC/TSOP II Pinout Top View Electrical Characteristics Over the Operating Range Maximum RatingsOperating Range AC Test Loads and Waveforms Data Retention Characteristics Over the Operating RangeThermal Resistance Data Retention WaveformParameter Description 45 ns 55 ns Unit Min Read CycleWrite Cycle Read Cycle No OE Controlled 17 Switching WaveformsRead Cycle No Address Transition Controlled 16 Write Cycle No WE Controlled, OE High During Write 19Write Cycle No CE Controlled 19 IO’s Mode PowerTruth Table Write Cycle No WE Controlled, OE LOWPackage Diagrams Ordering InformationPin 450 MIL Molded Soic Document Number Document HistoryDocument Title CY62148E MoBL , 4-Mbit 512K x 8 Static RAM REV ECN no