Cypress CY62148E manual Logic Block Diagram, Pin Configuration 2, Pin SOIC/TSOP II Pinout Top View

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CY62148E MoBL®

Logic Block Diagram

 

 

 

 

 

 

 

 

A0

 

INPUT BUFFER

 

 

IO0

A1

 

 

 

 

 

 

 

 

A2

 

 

 

 

 

 

 

IO1

A3

DECODER

 

512K x 8

 

 

AMPS

A6

 

 

 

IO3

A4

 

 

 

 

 

 

 

IO2

A5

 

 

 

 

 

 

 

 

A7

ROW

 

 

 

 

 

SENSE

 

A8

 

ARRAY

 

 

IO4

A9

 

 

 

 

 

 

 

 

A10

 

 

 

 

 

 

 

IO5

A11

 

 

 

 

 

 

 

 

A12

 

 

 

 

 

 

 

IO6

CE

COLUMN DECODER

POWER

IO7

WE

 

 

 

 

 

 

DOWN

 

OE

13

14

15

16

17

18

 

 

 

 

 

 

A

A

A

A

A

A

 

 

Pin Configuration [2, 4]

32-pin SOIC/TSOP II Pinout

Top View

A17

A16

A14

A12

A7 A6 A5 A4 A3 A2 A1 A0 IO0 IO1 IO2

VSS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

32

 

VCC

 

 

 

 

A

31

 

 

A15

30

 

18

29

 

 

WE

 

28

 

A13

 

27

 

 

A8

 

 

 

 

A

26

 

 

A9

25

 

11

 

 

 

 

 

24

 

 

OE

 

23

 

A10

 

22

 

CE

 

21IO7 IO6 IO5 IO4

IO320191817

Note

4. NC pins are not connected on the die.

Document #: 38-05442 Rev. *F

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Contents Tsop FeaturesProduct Portfolio Functional Description SoicPin SOIC/TSOP II Pinout Top View Logic Block DiagramPin Configuration 2 Operating Range Electrical Characteristics Over the Operating RangeMaximum Ratings AC Test Loads and Waveforms Data Retention Characteristics Over the Operating RangeThermal Resistance Data Retention WaveformWrite Cycle Parameter Description 45 ns 55 ns Unit MinRead Cycle Read Cycle No OE Controlled 17 Switching WaveformsRead Cycle No Address Transition Controlled 16 Write Cycle No WE Controlled, OE High During Write 19Write Cycle No CE Controlled 19 IO’s Mode PowerTruth Table Write Cycle No WE Controlled, OE LOWPackage Diagrams Ordering InformationPin 450 MIL Molded Soic Document Number Document HistoryDocument Title CY62148E MoBL , 4-Mbit 512K x 8 Static RAM REV ECN no