Design Considerations (Continued)
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| TABLE IV. Memory Map of HPC167064 Emulating an HPC16083 |
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FFFF:FFF0 | Interrupt Vectors |
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| 0128 |
| ENUR Register |
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FFEF:FFD0 | JSRP Vectors |
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| 0126 |
| TBUF Register |
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FFCF:FFCE |
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| 0124 |
| RBUF Register | UART | |
: | : |
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| 0122 |
| ENUI Register |
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E001:E000 |
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| User Memory |
| 0120 |
| ENU Register |
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DFFF:DFFE |
| External Expansion |
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| 0104 |
| Port D Input Register |
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| 00F5:00F4 | BFUN Register |
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: | : |
| Memory |
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| Ports A & B | |||
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| 00F3:00F2 | DIR B Register | |||||
0201:0200 |
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| 00F1:00F0 | DIR A Register /IBUF | ||||
01FF:01FE | ( |
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| 00E6 |
| UPIC Register | UPI Control | |||
: | : | User RAM |
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01C1:01C0 |
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| 00E3:00E2 | Port B | Ports A & B | |||
0195:0194 | WATCHDOG Register | WATCHDOG Logic |
| 00E1:00E0 | Port A/OBUF | |||||
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| 00DE |
| Reserved |
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0192 |
| T0CON Register |
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| 00DD:00DC | HALT Enable Register |
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0191:0190 | TMMODE Register |
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| Port Control | ||||||
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| 00D8 |
| Port I Input Register | ||||||
018F:018E | DIVBY Register |
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| 00D6 |
| SIO Register | ||||||
018D:018C | T3 Timer |
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| Control | ||||||
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| 00D4 |
| IRCD Register | |||||
018B:018A | R3 Register |
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| Timer Block T0:T3 |
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| 00D2 |
| IRPD Register | ||||||
0189:0188 | T2 Timer |
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| 00D0 |
| ENIR Register |
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0187:0186 | R2 Register |
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0185:0184 | I2CR Register/R1 |
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| 00CF:00CE | X Register |
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0183:0182 | I3CR Register/T1 |
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| 00CD:00CC | B Register |
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0181:0180 | I4CR Register |
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| 00CB:00CA | K Register |
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015E:015F | EICR |
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| 00C9:00C8 | A Register | HPC Core | |||
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| 00C7:00C6 | PC Register | Registers | |||||
015C |
| EICON |
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| 00C5:00C4 | SP Register |
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0153:0152 | Port P Register |
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| 00C3:00C2 | Reserved |
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0151:0150 | PWMODE Register |
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| 00C0 |
| PSW Register |
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014F:014E | R7 Register |
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014D:014C | T7 Timer |
| Timer Block T4:T7 |
| 00BF:00BE |
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014B:014A | R6 Register |
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0149:0148 | T6 Timer |
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| 0001:0000 |
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0147:0146 | R5 Register |
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0145:0144 | T5 Timer |
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0143:0142 | R4 Register |
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0141:0140 | T4 Timer |
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26