National Instruments HPC467064 Delay from CKI Rising Edge to ALE Rising Edge, ALE Pulse Width

20 MHz

AC Electrical Characteristics (Continued)

(See Notes 1 and 4 and Figures 1 thru 5 .) VCC e 5V g5%*, TA e b55§C to a125§C for HPC167064 and VCC e 5V g10%, TA e 0§C to a70§C for HPC467064 (Continued)

	Symbol and Formula		Parameter	Min	Max	Units	Notes
Cycles	tDC1ALER	Delay from CKI Rising Edge to ALE Rising Edge		0	35	ns	(Notes 1, 2)
	tDC1ALEF	Delay from CKI Rising Edge to ALE Falling Edge		0	35	ns	(Notes 1, 2)
	tDC2ALER e (/4 tC a 20	Delay from CK2 Rising Edge to ALE Rising Edge			45	ns
Address	tDC2ALEF e (/4 tC a 20	Delay from CK2 Falling Edge to ALE Falling Edge			45	ns
	tLL e (/2 tC b 9	ALE Pulse Width		41		ns
	tST e (/4 tC b 7	Setup of Address Valid before ALE Falling Edge		18		ns
	tVP e (/4 tC b 5	Hold of Address Valid after ALE Falling Edge		20		ns
	tARR e (/4 tC b 5
		ALE Falling Edge to RD Falling Edge		20		ns
Cycles	tACC e tC a WS b 55	Data Input Valid after Address Output Valid			145	ns
	tRD e (/2 tC a WS b 65
		Data Input Valid after RD Falling Edge			85	ns
Read	tRW e (/2 tC a WS b 10
		RD Pulse Width		140		ns
	tDR e */4 tC b 15
		Hold of Data Input Valid after RD Rising Edge		0	60	ns
	tRDA e tC b 15
		Bus Enable after RD Rising Edge		85		ns
Cycles	tWW e */4 tC a WS b 15			160		ns
		WR Pulse Width
	tARW e (/2 tC b 5	ALE Falling Edge to WR Falling Edge		45		ns
Write
	tV e (/2 tC a WS b 5
		Data Output Valid before WR Rising Edge		145		ns
	tHW e (/4 tC b 5
		Hold of Data Valid after WR Rising Edge		20		ns
	tDAR e (/4 tC a WS b 50
Ready Input		Falling Edge of ALE to Falling Edge of RDY			75	ns
	tRWR e tC
		RDY Pulse Width		100		ns

4