National Instruments HPC467064 HPC167064 CPU, Addressing Modes, HPC Instruction Set Description

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HPC167064 CPU

The HPC167064 CPU has a 16-bit ALU and six 16-bit regis- ters.

Arithmetic Logic Unit (ALU)

The ALU is 16 bits wide and can do 16-bit add, subtract and shift or logic AND, OR and exclusive OR in one timing cycle. The ALU can also output the carry bit to a 1-bit C register.

Accumulator (A) Register

The 16-bit A register is the source and destination register for most I/O, arithmetic, logic and data memory access op- erations.

Address (B and X) Registers

The 16-bit B and X registers can be used for indirect ad- dressing. They can automatically count up or down to se- quence through data memory.

Boundary (K) Register

The 16-bit K register is used to set limits in repetitive loops of code as register B sequences through data memory.

Stack Pointer (SP) Register

The 16-bit SP register is the pointer that addresses the stack. The SP register is incremented by two for each push or call and decremented by two for each pop or return. The stack can be placed anywhere in user memory and be as deep as the available memory permits.

Program (PC) Register

The 16-bit PC register addresses program memory.

Addressing Modes

ADDRESSING MODES—ACCUMULATOR AS DESTINATION

Register Indirect

This is the ‘‘normal’’ mode of addressing for the HPC167064 (instructions are single-byte). The operand is the memory addressed by the B register (or X register for some instructions).

Direct

The instruction contains an 8-bit or 16-bit address field that directly points to the memory for the operand.

Indirect

The instruction contains an 8-bit address field. The contents of the WORD addressed points to the memory for the oper- and.

Indexed

The instruction contains an 8-bit address field and an 8- or 16-bit displacement field. The contents of the WORD ad- dressed is added to the displacement to get the address of the operand.

Immediate

The instruction contains an 8-bit or 16-bit immediate field that is used as the operand.

Register Indirect (Auto Increment and Decrement)

The operand is the memory addressed by the X register. This mode automatically increments or decrements the X register (by 1 for bytes and by 2 for words).

Register Indirect (Auto Increment and Decrement) with Conditional Skip

The operand is the memory addressed by the B register. This mode automatically increments or decrements the B register (by 1 for bytes and by 2 for words). The B register is then compared with the K register. A skip condition is gener- ated if B goes past K.

ADDRESSING MODES—DIRECT MEMORY AS DESTINATION

Direct Memory to Direct Memory

The instruction contains two 8- or 16-bit address fields. One field directly points to the source operand and the other field directly points to the destination operand.

Immediate to Direct Memory

The instruction contains an 8- or 16-bit address field and an 8- or 16-bit immediate field. The immediate field is the oper- and and the direct field is the destination.

Double Register Indirect Using the B and X Registers Used only with Reset, Set and IF bit instructions; a specific bit within the 64 kbyte address range is addressed using the B and X registers. The address of a byte of memory is formed by adding the contents of the B register to the most significant 13 bits of the X register. The specific bit to be modified or tested within the byte of memory is selected using the least significant 3 bits of register X.

HPC Instruction Set Description

Mnemonic

Description

Action

ARITHMETIC INSTRUCTIONS

 

ADD

Add

MAaMemIxMA carryxC

ADC

Add with carry

MAaMemIaCMA carryxC

ADDS

Add short imm8

Aaimm8xA carryxC

DADC

Decimal add with carry

MAaMemIaCxMA (Decimal) carryxC

SUBC

Subtract with carry

MAbMemIaCxMA carryxC

DSUBC

Decimal subtract w/carry

MAbMemIaCxMA (Decimal) carryxC

MULT

Multiply (unsigned)

MA*MemIxMA & X, 0xK, 0xC

DIV

Divide (unsigned)

MA/MemIxMA, remxX, 0xK, 0xC

DIVD

Divide Double Word (unsigned)

X & MA/MemIxMA, remxX, 0xK, carryxC

IFEQ

If equal

Compare MA & MemI, Do next if equal

IFGT

If greater than

Compare MA & MemI, Do next if MA l MemI

AND

Logical AND

MA and MemIxMA

OR

Logical OR

MA or MemIxMA

XOR

Logical Exclusive-OR

MA xor MemIxMA

MEMORY MODIFY INSTRUCTIONS

 

INC

Increment

Mem a 1xMem

DECSZ

Decrement, skip if 0

Mem b1xMem, Skip next if Mem e 0

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Contents Features General DescriptionDC Electrical Characteristics ResetAbsolute Maximum Ratings ALL Other Inputs20 MHz AC Electrical Characteristics UPIDelay from CKI Rising Edge to ALE Rising Edge Delay from CKI Rising Edge to ALE Falling EdgeDelay from CK2 Rising Edge to ALE Rising Edge Delay from CK2 Falling Edge to ALE Falling Edge30 MHz AC Electrical Characteristics CKI Input Signal Characteristics CK1, CK2, ALE Timing Diagram Input and Output for AC TestsRead Cycle Microwire Setup/Hold Timing Eprom Mode Normal Running ModeFunctional Modes of Operation EconaErasure Characteristics Memory Map of the HPC167064Pin Descriptions Connection Diagram Ports a & BPorts a & B Operating Modes Power Save Modes HPC167064 Operating ModesWait States HPC167064 InterruptsBit External Memory Timer Overview Interrupt ArbitrationInterrupt Processing Interrupt Control RegistersBlock Diagram of Interrupt Logic Timers T2 T3 Block Synchronous OutputsTimer Registers Timer ApplicationsMICROWIRE/PLUS Operation Watchdog LogicMICROWIRE/PLUS MICROWIRE/PLUS ApplicationUart Wake-Up Mode HPC167064 UartShared Memory Support Universal Peripheral InterfaceMemory Design Considerations Table IV. Memory Map of HPC167064 Emulating an HPC16083 DfffdffeXtal Frequency MHz 1500 1200 910 750 600 470 390 300 220 180 100Addressing Modes HPC167064 CPUHPC Instruction Set Description BIT Instructions Sbit RbitIfbit Memory Transfer InstructionsCode Efficiency Development SupportHOW to Order Programming SupportHPC-DEV-IBMA HPC-DEV-IBMCPart Selection Socket SelectionPlcc YamaichiPage Physical Dimensions inches millimeters Life Support Policy
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