National Instruments HPC167064, HPC467064 manual Connection Diagram, Ports a & B

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Connection Diagram

TL/DD/11046 – 17

Top View

Order Number HPC167064, EL

See NS Package Number EL68C

Ports A & B

The highly flexible A and B ports are similarly structured. The Port A (see Figure 11 ), consists of a data register and a direction register. Port B (see Figures 12 thru Figure 14 ) has an alternate function register in addition to the data and direction registers. All the control registers are read/write registers.

The associated direction registers allow the port pins to be individually programmed as inputs or outputs. Port pins se- lected as inputs are placed in a TRI-STATE mode by reset- ting corresponding bits in the direction register.

A write operation to a port pin configured as an input causes the value to be written into the data register, a read opera- tion returns the value of the pin. Writing to port pins config- ured as outputs causes the pins to have the same value, reading the pins returns the value of the data register.

Primary and secondary functions are multiplexed onto Port B through the alternate function register (BFUN). The sec- ondary functions are enabled by setting the corresponding bits in the BFUN register.

TL/DD/11046 – 19

FIGURE 11. Port A: I/O Structure

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Contents General Description FeaturesReset DC Electrical CharacteristicsAbsolute Maximum Ratings ALL Other InputsUPI 20 MHz AC Electrical CharacteristicsDelay from CKI Rising Edge to ALE Falling Edge Delay from CKI Rising Edge to ALE Rising EdgeDelay from CK2 Rising Edge to ALE Rising Edge Delay from CK2 Falling Edge to ALE Falling Edge30 MHz AC Electrical Characteristics CKI Input Signal Characteristics Input and Output for AC Tests CK1, CK2, ALE Timing DiagramRead Cycle Microwire Setup/Hold Timing Normal Running Mode Eprom ModeFunctional Modes of Operation EconaMemory Map of the HPC167064 Erasure CharacteristicsPin Descriptions Ports a & B Connection DiagramPorts a & B Operating Modes HPC167064 Operating Modes Power Save ModesWait States HPC167064 InterruptsBit External Memory Interrupt Arbitration Timer OverviewInterrupt Processing Interrupt Control RegistersBlock Diagram of Interrupt Logic Synchronous Outputs Timers T2 T3 BlockTimer Applications Timer RegistersMICROWIRE/PLUS Operation Watchdog LogicMICROWIRE/PLUS Application MICROWIRE/PLUSHPC167064 Uart Uart Wake-Up ModeShared Memory Support Universal Peripheral InterfaceMemory Design Considerations Dfffdffe Table IV. Memory Map of HPC167064 Emulating an HPC16083Frequency MHz 1500 1200 910 750 600 470 390 300 220 180 100 XtalAddressing Modes HPC167064 CPUHPC Instruction Set Description Rbit BIT Instructions SbitIfbit Memory Transfer InstructionsDevelopment Support Code EfficiencyProgramming Support HOW to OrderHPC-DEV-IBMA HPC-DEV-IBMCSocket Selection Part SelectionPlcc YamaichiPage Life Support Policy Physical Dimensions inches millimeters