CyClone COMPACTPCI-824 user manual Physical Attributes, PMC Module Signal Definitions

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APPENDIX A

PMC MODULE INTERFACE

A.1 INTRODUCTION

The PMC Module Interface allows PCI devices to be connected to the Local PCI interface of the CPCI- 824 host. The IEEE STD P1386.1, PCI Mezzanine Card (PMC), provides for one set of clocking and arbitration signals per PMC Module. Cyclone Microsystems has expanded this to two sets per PMC Module on the CPCI-824. With ability to connect a PMC module on the CPCI-824, up to two devices are supported. Otherwise, with a few exceptions, the standard signals defined for 64-bit CPCI connectors are used for the PMC Modules. The exceptions are noted in Section A.3. The timing for devices on PMC Modules is the same as the timing for any other PCI device; see the PCI Local Bus Specification revision 2.2 for details. The CPCI-824 PMC module location is defined as +3.3V signalling. Note that only +3.3V or universal signalling PMC modules may be used on the CPCI-824.

A number of PMC Modules are available from Cyclone Microsystems. This section is intended for users interested in developing their own modules.

A.2 PHYSICAL ATTRIBUTES

Please refer to IEEE P1386/Draft 2.0 for the physical dimensions of PMC modules.

A.3 PMC MODULE SIGNAL DEFINITIONS

PMC Modules use the signals defined in the IEEE STD P1386.1. The following four signals are added to this definition to handle the expansion from one to two devices per PMC module:

•GNT1#

•REQ1#

•CLK1

•IDSEL1

Please note that the added signals used the PMC-RSVD signals as defined in IEEE STD P1386.1. The PCI-RSVD remain untouched.

Also, note that GNT1# follows the description for GNT#, REQ1# follows the description for REQ#, CLK1 follows the description for CLK, and IDSEL1 follows the description for IDSEL. When the appropriate signals are connected to PCI devices on a PMC Module, each device has the full complement of PCI signals defined in the specification.

IDSEL signals are not provided. The designer of a PMC Module should connect the proper AD signal to a device’s IDSEL pin. AD21:16 may be used depending on the desired number mapping scheme. The suggested signal connections are shown in tables A-1 and A-2.

CPCI-824 User’s Manual

A-1

Revision 1.0, January 2006

 

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Contents Page Appendix a ContentsChapter Appendix BList of Figures List of TablesContents CPCI-824 Block Diagram IntroductionGeneral Introduction Features SdramEnvironmental Specifications General Introduction SpecificationsEnvironmental CPCI-824 Physical Configuration General IntroductionReference Manuals Applied Micro Circuits CorporationSoftware Development Hardware Amcc Powerpc 440GX ProcessorByte Ordering Hardware Memory MAP DDR Sdram InterfaceSdram DDR DDR SdramInterrupts Input External InterruptsInterrupt Console Serial PortEthernet Console Serial Port Connector Pin Signal DescriptionGigabit Ethernet Port Fast Ethernet Port 100 Fast Port Connector Pin Signal Description 10/100Base-TGigabit Ethernet Port LEDs Fast Ethernet Port LEDsLeds Hardware Peripheral BUSFlash ROM User LEDs During InitializationLED Tests Breeze Start-up LedsGeographic Addressing FAN Monitoring Power Supply Monitoring10 I2C BUS Sdram Eeprom Jtag Emulator SupportJtag Emulator Pin Assignment Signal PMC Module Signal Definitions Physical AttributesModule Idsel Addr IDSEL# Clock Arbitration PMC Module ConnectorPMC Module Interface ST Device ND DeviceTable A-3. P21 PMC Module Connector Pinout Table A-4. P22 PMC Module Connector Pinout Signal Table A-5. P23 PMC Module Connector Pinout Appendix B Cpci J2 Definition Table B-1 CPCI-824 J2 Definition
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