SOYO P4X400 specifications CPU & PCI Bus Control

BIOS Setup Utility SY-P4X400 DRAGON Lite

3-4.2 CPU & PCI Bus Control

Caution: Change these settings only if you are already familiar with the Chipset.

The [CPU & PCI Bus Control] option changes the values of the chipset registers. These registers control the system options in the computer.

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CPU & PCI Bus Control

CPU to PCI Write Buffer	Enabled	Item Help
PCI Master 0 WS Write	Enabled
		Menu Level
PCI Delay Transaction	Disabled
VLink 8X Support	Enabled

:Move	Enter:Select	+/-/PU/PD:Value	F10:Save	ESC:Exit	F1:General Help
F5:Previous Values		F6:Fail-Safe Defaults		F7: Optimized Defaults

After you have completed the changes, press [Esc] and follow the instructions on your screen to save your settings or exit without saving.

CPU & PCI Bus Control

	Setting	Description	Note
CPU to PCI
	Disabled
Write Buffer	Enabled	Enabled the CPU to PCI Write	Default
PCI Master 0		Buffer.
	Disabled	This item allows you to
WS Write	Enabled	enabled/disabled the PCI post write.	Default
PCI Delay
	Disabled	The chipset has an embedded 32-bit	Default
Transaction	Enabled	posted write buffer to support delay
		transactions cycles. Select Enabled
		to support compliance with PCI
		specification version 2.1.
VLink 8X
	Disabled	Enabled item can support Quad Data
Support	Enabled	Transfer interconnect to the VT8235	Default
		South Bridge.

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