Transcend Information
TS64GSSD25-M, TS128GSSD25-M Device terminating an Ultra DMA data-in burst
Specs
Block Diagram
Dimension
Support ATA/ATAPI Command List
Security Disable Password F6h
SET Multiple Mode
Page 34
TS8GSSD25-S
TS16GSSD25-S
TS32GSSD25-S/M
TS64GSSD25-S/M
2.5” Solid State Disk
TS128GSSD25-M
Device terminating an Ultra DMA
data-in
burst
Transcend Information Inc.
34
V1.08
Page 33
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Contents
Description
Placement Features
Dimensions
V1.08
Specifications
Sequential WriteMax
Model P/N Sequential ReadMax
Model P/N User Max. LBA Cylinder Head Sector
Operating Non-Operating
Data Reliability Data Retention
Compliance
Package Dimensions
TS128GSSD25-M
Pin Layout
Pin Assignments
Pin No Pin Name
Block Diagram
ECC algorithm
Reliability
Wear-Leveling algorithm
Bad-block management
Support ATA/ATAPI Command List
Command Name Code
SET Multiple Mode
ATA Command Specifications
Identify Device Information Default Value
Word Value Description
PIO data transfer cycle timing mode Reserved
TS8GSSD25-S TS16GSSD25-S TS32GSSD25-S/M TS64GSSD25-S/M
Minor version number
TS8GSSD25-S TS16GSSD25-S TS32GSSD25-S/M TS64GSSD25-S/M
TS8GSSD25-S TS16GSSD25-S TS32GSSD25-S/M TS64GSSD25-S/M
TS8GSSD25-S TS16GSSD25-S TS32GSSD25-S/M TS64GSSD25-S/M
Initialize Device Parameters 91h
Idle E3h
Idle Immediate E1h
Read Buffer E4h
Read Multiple C4h
Log Address Log Name Feature Set Access
Read LOG EXT 2Fh
Read Multiple EXT 29h
Security Erase Prepare F3h
Security Disable Password F6h
Recalibrate 10h
Security Erase Unit F4h
Security set Password data content
Security Unlock information
Features register Value and settable operating mode
Byte Description
D9h
DAh
Byte 2-361 Individual attribute data
Attribute ID information is listed in the following table
Description Detail Information Byte
Smart Read Attribute Threshold
Smart Enabl Operations
Write Buffer E8h
Standby E2h
Standby Immediate E0h
Write DMA CAh
Write Sectors 30h/31h
Write Multiple EXT 39h
Write Multiple FUA EXT CEh
Write Sectors EXT 34h
Transcend Information Inc
Ultra DMA data transfer
Ultra DMA data burst timing requirements
Name Comment
Initiating an Ultra DMA data-in burst
Host pausing an Ultra DMA data-in burst
Sustained Ultra DMA data-in burst
Device terminating an Ultra DMA data-in burst
Host terminating an Ultra DMA data-in burst
Initiating an Ultra DMA data-out burst
Device pausing an Ultra DMA data-out burst
Sustained Ultra DMA data-out burst
Host terminating an Ultra DMA data-out burst
Device terminating an Ultra DMA data-out burst
PIO data transfer
PIO timing requirements
PIO data transfer to/from device
Ordering Information
Taiwan Germany
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