Transcend Information TS64GSSD25-M, TS128GSSD25-M dimensions Ordering Information, Taiwan Germany

Page 42

TS8GSSD25-S

 

TS16GSSD25-S

 

TS32GSSD25-S/M

 

TS64GSSD25-S/M

2.5” Solid State Disk

TS128GSSD25-M

Ordering Information

 

The above technical information is based on industry standard data and has been tested to be reliable. However, Transcend makes no warranty, either expressed or implied, as to its accuracy and assumes no liability in connection with the use of this product. Transcend reserves the right to make changes to the specifications at any time without prior notice.

 

 

USA

 

 

Los Angeles:

 

 

E-mail: sales@transcendusa.com

 

 

Maryland:

 

 

E-mail: sales_md@transcendusa.com

 

 

www.transcendusa.com

 

 

CHINA

 

 

E-mail: sales@transcendchina.com

 

 

www.transcendchina.com

TAIWAN

 

GERMANY

No.70, XingZhong Rd., NeiHu Dist., Taipei, Taiwan, R.O.C

E-mail: vertrieb@transcend.de

TEL +886-2-2792-8000

 

www.transcend.de

Fax +886-2-2793-2222

 

HONG KONG

E-mail: sales@transcend.com.tw

 

E-mail: sales@transcend.com.hk

www.transcend.com.tw

 

www.transcendchina.com

 

 

JAPAN

 

 

E-mail: sales@transcend.co.jp

 

 

www.transcend.jp

 

 

THE NETHERLANDS

 

 

E-mail: sales@transcend.nl

 

 

www.transcend.nl

 

 

United Kingdom

 

 

E-mail: sales@transcend-uk.com

 

 

www.transcend-uk.com

 

 

KOREA

 

 

E-mail: sales@transcend.kr

 

 

www.transcend.co.kr

 

 

 

Transcend Information Inc.

42

 

V1.08

Image 42
Contents Description Placement FeaturesDimensions V1.08Specifications Model P/N Sequential ReadMax Sequential WriteMaxModel P/N User Max. LBA Cylinder Head Sector Data Reliability Data Retention Operating Non-OperatingCompliance Package Dimensions TS128GSSD25-MPin Assignments Pin LayoutPin No Pin Name Block Diagram ECC algorithm ReliabilityWear-Leveling algorithm Bad-block managementSupport ATA/ATAPI Command List Command Name CodeSET Multiple Mode ATA Command Specifications Identify Device Information Default Value Word Value DescriptionPIO data transfer cycle timing mode Reserved TS8GSSD25-S TS16GSSD25-S TS32GSSD25-S/M TS64GSSD25-S/M Minor version number TS8GSSD25-S TS16GSSD25-S TS32GSSD25-S/M TS64GSSD25-S/M TS8GSSD25-S TS16GSSD25-S TS32GSSD25-S/M TS64GSSD25-S/M TS8GSSD25-S TS16GSSD25-S TS32GSSD25-S/M TS64GSSD25-S/M Initialize Device Parameters 91h Idle E3hIdle Immediate E1h Read Buffer E4hRead Multiple C4h Log Address Log Name Feature Set AccessRead LOG EXT 2Fh Read Multiple EXT 29hSecurity Erase Prepare F3h Security Disable Password F6hRecalibrate 10h Security Erase Unit F4hSecurity set Password data content Security Unlock informationFeatures register Value and settable operating mode Byte Description D9hDAh Byte 2-361 Individual attribute dataAttribute ID information is listed in the following table Description Detail Information ByteSmart Read Attribute Threshold Smart Enabl Operations Write Buffer E8h Standby E2hStandby Immediate E0h Write DMA CAhWrite Sectors 30h/31h Write Multiple EXT 39hWrite Multiple FUA EXT CEh Write Sectors EXT 34hUltra DMA data transfer Transcend Information IncUltra DMA data burst timing requirements Name Comment Initiating an Ultra DMA data-in burst Host pausing an Ultra DMA data-in burst Sustained Ultra DMA data-in burstDevice terminating an Ultra DMA data-in burst Host terminating an Ultra DMA data-in burst Initiating an Ultra DMA data-out burst Device pausing an Ultra DMA data-out burst Sustained Ultra DMA data-out burstHost terminating an Ultra DMA data-out burst Device terminating an Ultra DMA data-out burst PIO data transfer PIO timing requirementsPIO data transfer to/from device Ordering Information Taiwan Germany