Transcend Information TS128GSSD25-M, TS16GSSD25-S PIO data transfer, PIO timing requirements

Page 40

 

TS8GSSD25-S

 

 

 

 

 

 

 

 

TS16GSSD25-S

 

 

 

 

 

 

 

 

TS32GSSD25-S/M

 

 

 

 

 

 

 

 

TS64GSSD25-S/M

 

 

 

2.5” Solid State Disk

 

TS128GSSD25-M

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PIO data transfer

PIO timing requirements

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PIO timing parameters

 

Mode 0

Mode 1

Mode 2

Mode 3

Mode 4

 

 

 

 

 

ns

ns

ns

ns

ns

 

 

t0

Cycle time

(min)

600

383

240

180

120

 

 

t1

Address valid to DIOR-/DIOW- setup

(min)

70

50

30

30

25

 

 

t2

DIOR-/DIOW-

(min)

165

125

100

80

70

 

 

t2i

DIOR-/DIOW- recovery time

(min)

-

-

-

70

25

 

 

t3

DIOW- data setup

(min)

60

45

30

30

20

 

 

t4

DIOW- data hold

(min)

30

20

15

10

10

 

 

t5

DIOR- data setup

(min)

50

35

20

20

20

 

 

t6

DIOR- data hold

(min)

5

5

5

5

5

 

 

t6Z

DIOR- data tristate

(max)

30

30

30

30

30

 

 

t9

DIOR-/DIOW- to address valid hold

(min)

20

15

10

10

10

 

 

tRD

Read Data Valid to IORDY active

(min)

0

0

0

0

0

 

 

 

(if IORDY initially low after tA)

 

 

 

 

 

 

 

 

tA

IORDY Setup time

 

35

35

35

35

35

 

 

tB

IORDY Pulse Width

(max)

1250

1250

1250

1250

1250

 

 

tC

IORDY assertion to release

(max)

5

5

5

5

5

 

Transcend Information Inc.

40

V1.08

Image 40
Contents Placement Features DimensionsDescription V1.08Specifications Sequential WriteMax Model P/N Sequential ReadMaxModel P/N User Max. LBA Cylinder Head Sector Operating Non-Operating Data Reliability Data RetentionCompliance Package Dimensions TS128GSSD25-MPin Layout Pin AssignmentsPin No Pin Name Block Diagram Reliability Wear-Leveling algorithmECC algorithm Bad-block managementSupport ATA/ATAPI Command List Command Name CodeSET Multiple Mode ATA Command Specifications Identify Device Information Default Value Word Value DescriptionPIO data transfer cycle timing mode Reserved TS8GSSD25-S TS16GSSD25-S TS32GSSD25-S/M TS64GSSD25-S/M Minor version number TS8GSSD25-S TS16GSSD25-S TS32GSSD25-S/M TS64GSSD25-S/M TS8GSSD25-S TS16GSSD25-S TS32GSSD25-S/M TS64GSSD25-S/M TS8GSSD25-S TS16GSSD25-S TS32GSSD25-S/M TS64GSSD25-S/M Idle E3h Idle Immediate E1hInitialize Device Parameters 91h Read Buffer E4hLog Address Log Name Feature Set Access Read LOG EXT 2FhRead Multiple C4h Read Multiple EXT 29hSecurity Disable Password F6h Recalibrate 10hSecurity Erase Prepare F3h Security Erase Unit F4hSecurity set Password data content Security Unlock informationFeatures register Value and settable operating mode D9h DAhByte Description Byte 2-361 Individual attribute dataAttribute ID information is listed in the following table Description Detail Information ByteSmart Read Attribute Threshold Smart Enabl Operations Standby E2h Standby Immediate E0hWrite Buffer E8h Write DMA CAhWrite Multiple EXT 39h Write Multiple FUA EXT CEhWrite Sectors 30h/31h Write Sectors EXT 34hTranscend Information Inc Ultra DMA data transferUltra DMA data burst timing requirements Name Comment Initiating an Ultra DMA data-in burst Host pausing an Ultra DMA data-in burst Sustained Ultra DMA data-in burstDevice terminating an Ultra DMA data-in burst Host terminating an Ultra DMA data-in burst Initiating an Ultra DMA data-out burst Device pausing an Ultra DMA data-out burst Sustained Ultra DMA data-out burstHost terminating an Ultra DMA data-out burst Device terminating an Ultra DMA data-out burst PIO data transfer PIO timing requirementsPIO data transfer to/from device Ordering Information Taiwan Germany