6.2.2. Timing of Host Interface (PIO)
Figure 10 shows the Host Interface Timings.
Address valid*1
t2 t1
Write data valid*2
Read data valid*2
t0
t9
t2i
t8
t3
t4
t5
t6Z
t7 |
| t6 |
|
IOCS16-
tA
IORDY
tB tRD
*1:Device Address consists of signals
| PIO Mode 4 timing parameters min(ns) max(ns) | Min Time (ns) | Max Time (ns) |
t0 | Cycle time | 120 |
|
t1 | Address valid to | 25 |
|
t2 | 70 |
| |
t2i | 25 |
| |
t3 | DIOW- data setup | 20 |
|
t4 | DIOW- data hold | 10 |
|
t5 | DIOR- data setup | 20 |
|
t6 | DIOR- data hold | 5 |
|
t6Z | DIOR- data tristate |
| 30 |
t7 | Addr valid to IOCS16- assertion |
| 30 |
t8 | Addr valid to IOCS16- negation |
| 30 |
t9 | 10 |
| |
tRD | Read Data Valid to IORDY active | 0 |
|
tA | IORDY setup time |
| 35 |
tB | IORDY pulse wide |
| 1250 |
Figure 10 Host Interface Timin
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|