Toshiba XM-7002B specifications 16/27, Shows the Host Interface DMA multi word Timings

6.2.3.Timing of Host Interface (DMA Multi)

Figure 11 shows the Host Interface DMA multi word Timings

		t0
DMARQ
		tL
DMACK-*1
	tD	tK
	tI	tJ
DIOR/DIOW-*1
Read	tE	tZ
DD0-1

tF

Write

DD0-1

tG tH

*1: In all timing diagrams, the low line indicator negated, and the upper line indicators asserted.

	Multi word DMA Mode 2	Min time (ns)	Max time (ns)
	timing parameters min (ns) max (ns)
t0	Cycle time	120
tC	DMACK to DMREQ delay		---
tD	DIOR-/DIOW- 16-bit	70
tE	DIOR- data access		50
tF	DIOR- data hold	5
tZ	DMACK- to tristate		25
tG	DIOR/DIOW- data setup	20
tH	DIOW- data hold	10
tI	DMACK to DIOR-/DIOW- setup	0
tJ	DIOR-/DIOW- to DMACK hold	5
tKr	DIOR- negated pulse width	25
tKw	DIOW- negated pulse width	25
tLr	DIOR- to DMREQ delay		35
tLw	DIOR- to DMREQ delay		35

Figure 11 Host Interface Timing (DMA Multi)

16/27 XM-7002B Rev.1.0