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| Common | 16:9 |
| YUV | Memory |
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| Service |
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| Stick |
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| Fix/ Var | No. | Name | Description |
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| Group | Init | Init |
| Init | Init |
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| Data | Data |
| Data | Data |
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| ASIC | Fix | 30 | HFFR | AFC1 FORCE FREERUN | 0 |
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| Fix | 31 | HFUP | H FREERUN FREQUENCY | 0 |
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| UP(700Hz) |
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| Fix | 32 | JSWW | Jump Pulse Width | 0 |
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| Fix | 33 | XF0A | VCXO FREERUN ADJUST | 0 |
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| Fix | 34 | BGST | BGP(for PLL) TIMING | 16 |
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| 6 | 6 |
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| Fix | 35 | XPHA | VCXO PHASE ADJUST | 10 |
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| Fix | 36 | HRMP | AFC2 TIME CONSTANT | 3 |
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| Fix | 37 | RPLU | REF PLL TIME CONSTANT | 3 |
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| Fix | 38 | RPLB | REF PLL TIME CONSTANT | 1 |
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| Fix | 39 | XF0B | VCXO Fo ADJUST | 0 |
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| Fix | 40 | RPLS | REF VCO FB LOOP SELECT | 0 |
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| Fix | 41 | SSM | SyncSepaMasking CONTROL | 0 |
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| Fix | 42 | VSAG | 0 |
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| Fix | 43 | AFC2 | AFC2 GAIN CONTROL | 0 |
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| Fix | 44 | VRFL | V RAMP FILTER SWITCHING OFF | 0 |
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| Fix | 45 | XPLU | ACP TIME CONSTANT | 1 |
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| Fix | 46 | CDM2 | V_LOGIC SW | 1 |
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| Fix | 47 | BGPC | BGP C | 0 |
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| Fix | 48 | MHDL | BGP SEL | 1 |
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| Fix | 49 | BFRE | force V FREERUN | 0 |
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| Fix | 50 | HRPP | FRAMP RRAMP H OUT CONTROL | 2 |
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| RANGE |
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| Fix | 51 | DSCK | DS DAC CLK SW for only Not YUV | 0 | 0 |
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| Fix | 52 | VBHK | V BLK HALF KILL only 16:9Off | 0 |
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| Fix | 53 | VPW | V Pulse Wide | 1 |
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| Fix | 54 | DTH | DITHER THRESHOLD LEVEL | 1 |
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| CONTROL at IIC AUTOD=ON |
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| Fix | 55 | SLON | LPF SYNC ON | 5 |
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| 5 | 5 |
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| Fix | 56 | VSSW | SYNC SLICE LEVEL(V) Wide | 0 |
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| Window |
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| Fix | 57 | AF2S | AFC2 timing SW | 0 |
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| Fix | 58 | VSL2 | Digital V_SYNC_LPF(fall) | 1 |
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| Fix | 59 | VSL1 | Digital V_SYNC_LPF(rise) | 0 |
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| Fix | 60 | VSHE | 0 |
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| Fix | 61 | DSCS | CLOCK DIV SEL | 1 |
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| 0 | 0 |
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| Fix | 62 | 14HI | 4fsc(Skew)CLK POLARITY | 0 |
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| Fix | 63 | 14HD | 4fscCLK(Skew)CLK DELAY ADJUST | 0 |
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| 36 |