CHAPTER 1 PRODUCT HANDLING AND SPECIFICATIONS
■Operation outline
Figure 1.9-2"Timing chart of the power-on debug operation" is a timing chart of the power-on debug operation.
❍Operation timing Detection of power-off:
Power-off status of user system power supply voltage (UVCC) is detected.
When the user power supply voltage becomes equal to or less than the power-off detection level, the emulator outputs an L-level signal to the PLEV pin of the evaluation MCU to stop the MCU and prevent its malfunction.
(See (1) in Figure 1.9-2"Timing chart of the power-on debug operation".)
Detection of power-on:
The power-on status of user system power supply voltage (UVCC) is detected.
Power-on of the user power supply (UVcc) is detected.
The function checks that a voltage higher than the power-off detection level is held for the operation stabilization time (about 2 ms) of the evaluation MCU after the voltage is detected as being higher than the power-off detection level.
(See (2) in Figure 1.9-2"Timing chart of the power-on debug operation".)
After the operation stabilization time, the emulator outputs an H-level signal to the PLEV pin of the evaluation MCU and releases the user reset input for program execution.
(See (3) in Figure 1.9-2"Timing chart of the power-on debug operation".)
Figure 1.9-2 Timing chart of the power-on debug operation
UVCC
Power-off detection level
(3)
Operation stabilization
time (2 ms)
PLEV
Notes:
Setting of the power-off detection level must take the characteristics of the user power supply (UVCC) into consideration.
If using the power-on debug function, generally set the voltage about 5% above the minimum operation assurance voltage of the evaluation MCU. If not using the power-on debug function, set the voltage to the minimum operation assurance voltage of the evaluation MCU. While the PLEV pin level is low, the emulator functions (trace, event, and other) are disabled because the evaluation MCU blocks the emulator connection to prevent the emulator from malfunctioning.
