TDA9141 has two input terminals for the composite video/Y signal (pin 25) and C signal (pin 26), and each of the signals is automatically identified through I2C- BUS control.
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| MED849 |
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V P2 | 1 | 16 | V |
N.C. | 2 | 15 | N.C. |
GND2 | 3 | 14 | V |
I.C. | 4 | 13 | N.C. |
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| TDA4665 | V |
SAND | 5 | 12 | |
N.C. | 6 | 11 | V |
I.C. | 7 | 10 | GND1 |
I.C. | 8 | 9 | V P1 |
Fig. 7-3-6 Pin configuration of TDA4665T
Table 7-3-2 Terminal function of TDA4665T
Pin No. | Name | Function | |
1 | VP2 | +5V power supply for | |
digital block | |||
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2 | N.C. | Not used | |
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3 | GND2 | GND (0V) for digital block | |
4 | I.C. | Internal connection | |
5 | SAND | Sandcastle pulse input | |
6 | N.C. | Not used | |
7 | I.C. | Internal connection | |
8 | I.C. | Internal connection | |
9 | VP1 | +5V power supply for | |
analog block | |||
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10 | GND1 | GND (0V) for analog | |
block | |||
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11 | ± | ||
12 | ± | ||
13 | N.C. | Not used | |
14 | ± | ||
15 | N.C. | Not used | |
16 | ± |
16 | SIGNAL |
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CLAMPING |
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| LINE |
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| 11 |
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| AND | LP |
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| MEMORY |
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| HOLD |
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Color | difference |
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input | signals |
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| Addition | Output | Color | difference | |||
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| stages | buffers | Output | signals | ||
14 | SIGNAL |
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CLAMPING |
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| LINE |
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| 12 |
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| AND | LP |
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| MEMORY |
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| HOLD |
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V P1 | 9 | analog supply |
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| 2 | N.C. |
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| 3 MHz shifting clock | TDA4665 |
| 6 | N.C. |
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| SANDCASTLE | FREQUENCY | DIVIDER |
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| 13 | N.C. |
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| 5 | PHASE |
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Sand castle | DETECTOR | BY 192 |
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| 15 | N.C. |
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| DETECTOR |
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pulse | input |
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| LP | 6 MHz | DIVIDER |
| 7 | I.C. |
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| CCO | BY 2 |
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| 10 |
| Digital | supply | 1 | 3 | 4 | 8 |
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| GND 1 |
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| GND 2 |
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| V P2 |
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| Fig. |
| MED848 |
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7-3-3. Luminance (Y) Signal Process Circuit
The processing method differs as follows depending on type of the signal entered.
(a)For a SECAM input, it passes through a burst signal trap circuit.
(b)For a NTSC/PAL (with burst signal) input
(c)For a NTSC/PAL (without burst signal) input, above trap circuit and the delay circuit are bypassed to per- form a stable color killer operation.