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| Pin | Name |
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| No. |
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This circuit separates Y and C signals from a composite |
| 1 | VREFH | ADC bias |
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video signal. Fig. |
| 2 | VSS1 | ADC GND |
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TC9090AN and Fig. |
| 3 | ADIN | Video input |
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The composite video signal enters pin 3. A fsc (3.58/ |
| 4 | VDD1 | ADC VDD |
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4.43 MHz) developed from the video/color IC enters pin |
| 5 | VREFL | ADC bias |
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19 and is converted into a 4fsc of the drive clock |
| 6 | BIAS1 | ADC bias |
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frequency inside the IC. The composite video signal |
| 7 | P/S |
| Selection function control | |||||||
entered is processed at a rate of the clock frequency of |
| 8 | SDA |
| I2C bus clock input |
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the IC and output as Y and C signal. |
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| 9 | SCL |
| I2C bus data input, check output | |||||
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| 10 | RESET | I2C bus reset |
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VREFH | 1 |
| 28 | VSS4 |
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| 11 | TEST1 | Test terminal |
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VSS1 | 2 |
| 27 | VDD4 |
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| 12 | TEST2 | Test terminal |
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ADIN | 3 |
| 26 | VREF1 |
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| 13 | KILLER | Clock killer switch |
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VDD1 | 4 |
| 25 | YOUT |
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| 14 | PLLSEL | Selection input clock | |||
VREFL | 5 |
| 24 | BIAS2 |
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| 15 | VDD3 | Digital VDD |
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BIAS1 | 6 |
| 23 | COUT |
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| 16 | VSS3 | Analog GND |
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P/S | 7 |
| 22 | BIAS3 |
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| 17 | VSS2 | PLL GND |
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SDA | 8 |
| 21 | 2/1VDD |
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| 18 | VDD2 | PLL VDD |
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SCL | 9 |
| 20 | VFIL |
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| 19 | CKIN | Clock input |
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RESET | 10 |
| 19 | CKIN |
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| 20 | VFIL | VCO filter |
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TEST1 | 11 |
| 18 | VDD2 |
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| 21 | 2/1 VDD | Line memory bias |
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TEST2 | 12 |
| 17 | VSS2 |
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| 22 | BIAS3 | DAC bias |
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KILLER | 13 |
| 16 | VSS3 |
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| 23 | COUT | C output |
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PLLSEL | 14 |
| 15 | VDD3 |
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| 24 | BIAS2 | DAC bias |
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| 25 | YOUT | Y output |
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Fig. |
| 26 | VREF1 | DAC bias |
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| 27 | VDD4 | DAC VDD |
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| 28 | VSS4 | DAC GND |
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Composite |
| ADC | LINE |
| VERTICAL EDGE |
| CORING |
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video signal 2 | MEMORY | ENHANCE CIRCUIT | CIRCUIT |
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| 8 bits |
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| CLAMP |
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| + | + | PEDESTAL | YDAC | 25 Y | |
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| CLIP | 8 bits | output | |||
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| COLOR KILLER CIRCUIT |
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| 4.43 MHz NTSC |
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| BPF |
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| BPF |
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| DYNAMIC | 1 LINE DOT |
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| 23 C | |
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| BPF | COMB |
| IMPROVE |
| BPF |
| CDAC | |
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| FILTER |
| CIRCUIT |
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| 8 bits | output |
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| BPF |
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Clock 19 |
| PLL |
| 4 FSC |
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| I2C BUS |
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| 8 | 9 |
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| Bus |
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| Fig. |
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