JAI CV-A33CL Column Process, CV-A33 Cmos Sensor array, Cmos Sensor principle diagram

CV-A33CL

6.1.3. Column Process
The voltage signal from a single pixel is send to the	Columns
column amplifier trough the 4 to 1 multiplexer. After							10 bit
the S/H circuit, the offset and gain calibrating is
							video
perform. A 10 bit A/D converter send the digital pixel					Offset		To shift
		Amp	S/H		Gain	A/D	Register
signal to the digital horizontal shift register by a 1 to 4					calibr		through
							1 to 4
multiplexing. Signals from a single row with 667 pixels							multiplex
				Control and timing
are processed in parallel and send to the shift register.
Control and timing is done from the timing block.
The calibrate command CB = 0 will start an automatic		Fig. 9. Column processing principle
calibrate routine for offset and gain for all 167 A/D
converter. It reduces the vertical fix pattern column noise.

6.1.4. CV-A33 CMOS Sensor array

The CMOS sensor total array is 667 (h) x 502 (v). Here the 659 (h) x 494 (v) is active photo sensing pixels. 8 pixels (h) and 8 rows (v) are optical black pixels for internal black level reference. There is an A/D converter for each 4 columns.

A 4 to 1 multiplexer feed the signals from 4 columns to a A/D converter. The digital converter output is multiplexed to the 667 x10 bit register.

Timing

(502,667)	667 Columns	8 rows and 8 columns
		optical dark pixels

decode	667 x 502 sensor array	502
Row	659 x 494 Active pixels	Rows
		(1,1)
	4 to 1 multiplexer
	167 x A/D converter	10 bit digital
	1 to 4 multiplexer
	667 x 10 bit register	Video out

Fig. 10. CV-A33 CMOS sensor array

6.1.5. CMOS Sensor principle diagram

Fig. 11. CMOS sensor principle diagram

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