Sony MDS-JB920 Xras, Xwe, Mvci, Asyo, Asyi, Avdd, Bias, Rfi, Avss, Fili, Filo, Cltv, Peak, AUX1

Page 34

Pin No.

Pin Name

I/O

Function

 

 

 

 

 

 

 

 

 

45

 

A09

O

Address signal output to the D-RAM (IC124)

 

 

 

 

 

 

 

 

 

46

 

XRAS

O

Row address strobe signal output to the D-RAM (IC124)

“L” active

 

 

 

 

 

 

 

47

 

XWE

O

Write enable signal output to the D-RAM (IC124)

“L” active

 

 

 

 

 

 

 

48

 

D1

I/O

 

 

 

 

 

 

 

 

 

 

49

 

D0

I/O

Two-way data bus with the D-RAM (IC124)

 

 

 

 

 

 

 

 

 

50

 

D2

I/O

 

 

 

 

 

 

 

 

 

 

 

 

 

51

 

D3

I/O

 

 

 

 

 

 

 

 

 

52

 

MVCI

I (S)

Digital in PLL oscillation input from the external VCO

Not used (fixed at “L”)

 

 

 

 

 

 

 

53

 

ASYO

O

Playback EFM full-swing output terminal

 

 

 

 

 

 

 

54

 

ASYI

I (A)

Playback EFM asymmetry comparator voltage input terminal

 

 

 

 

 

 

 

55

 

AVDD

—

Power supply terminal (+3.3V) (analog system)

 

 

 

 

 

 

 

56

 

BIAS

I (A)

Playback EFM asymmetry circuit constant current input terminal

 

 

 

 

 

57

 

RFI

I (A)

Playback EFM RF signal input from the CXA2523AR (IC101)

 

 

 

 

 

 

 

58

 

AVSS

—

Ground terminal (analog system)

 

 

 

 

 

 

 

59

 

PCO

O (3)

Phase comparison output for master clock of the recording/playback EFM master PLL

 

 

 

 

 

60

 

FILI

I (A)

Filter input for master clock of the recording/playback master PLL

 

 

 

 

 

61

 

FILO

O (A)

Filter output for master clock of the recording/playback master PLL

 

 

 

 

 

62

 

CLTV

I (A)

Internal VCO control voltage input of the recording/playback master PLL

 

 

 

 

 

63

 

PEAK

I (A)

Light amount signal (RF/ABCD) peak hold input from the CXA2523AR (IC101)

 

 

 

 

 

64

 

BOTM

I (A)

Light amount signal (RF/ABCD) bottom hold input from the CXA2523AR (IC101)

 

 

 

 

 

65

 

ABCD

I (A)

Light amount signal (ABCD) input from the CXA2523AR (IC101)

 

 

 

 

 

 

66

 

FE

I (A)

Focus error signal input from the CXA2523AR (IC101)

 

 

 

 

 

 

67

 

AUX1

I (A)

Auxiliary signal (I3 signal/temperature signal) input from the CXA2523AR (IC101)

 

 

 

 

 

68

 

VC

I (A)

Middle point voltage (+1.65V) input from the CXA2523AR (IC101)

 

 

 

 

 

 

69

 

ADIO

O (A)

Monitor output of the A/D converter input signal

Not used (open)

 

 

 

 

 

 

 

70

 

AVDD

—

Power supply terminal (+3.3V) (analog system)

 

 

 

 

 

 

 

71

 

ADRT

I (A)

A/D converter operational range upper limit voltage input terminal (fixed at “H” in this set)

 

 

 

 

 

72

 

ADRB

I (A)

A/D converter operational range lower limit voltage input terminal (fixed at “L” in this set)

 

 

 

 

 

 

 

73

 

AVSS

—

Ground terminal (analog system)

 

 

 

 

 

 

 

 

74

 

SE

I (A)

Sled error signal input from the CXA2523AR (IC101)

 

 

 

 

 

 

75

 

TE

I (A)

Tracking error signal input from the CXA2523AR (IC101)

 

 

 

 

 

 

 

76

 

DCHG

I (A)

Connected to the +3.3V power supply

 

 

 

 

 

 

 

 

77

 

APC

I (A)

Error signal input for the laser automatic power control

Not used (fixed at “H”)

 

 

 

 

 

78

 

ADFG

I (S)

ADIP duplex FM signal (22.05 kHz ± 1 kHz) input from the CXA2523AR (IC101)

 

 

 

 

 

79

 

F0CNT

O

Filter f0 control signal output to the CXA2523AR (IC101)

 

 

 

 

 

80

 

XLRF

O

Serial data latch pulse signal output to the CXA2523AR (IC101)

 

 

 

 

 

81

 

CKRF

O

Serial data transfer clock signal output to the CXA2523AR (IC101)

 

 

 

 

 

 

82

 

DTRF

O

Writing serial data output to the CXA2523AR (IC101)

 

 

 

 

 

 

 

83

APCREF

O

Control signal output to the reference voltage generator circuit for the laser automatic power

control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

84

 

LDDR

O

PWM signal output for the laser automatic power control

Not used (open)

 

 

 

 

 

85

 

TRDR

O

Tracking servo drive PWM signal (–) output to the BH6511FS (IC152)

 

 

 

 

 

86

 

TFDR

O

Tracking servo drive PWM signal (+) output to the BH6511FS (IC152)

 

 

 

 

 

 

 

87

 

DVDD

—

Power supply terminal (+3.3V) (digital system)

 

 

 

 

 

 

 

88

 

FFDR

O

Focus servo drive PWM signal (+) output to the BH6511FS (IC152)

 

 

 

 

 

89

 

FRDR

O

Focus servo drive PWM signal (–) output to the BH6511FS (IC152)

 

 

 

 

 

 

90

 

FS4

O

Clock signal (176.4 kHz) output terminal (X’tal system)

Not used (open)

 

 

 

 

 

 

 

 

* I (S) stands for schmitt input, I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O.

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Page 33 Page 35
Contents MDS-JE520 SpecificationsMDM-5A SELF-DIAGNOSIS Function GeneralItems of Error History Mode Items and Contents Diagrams Table of ContentsSection Servicing Notes Varning Flexible Circuit Board RepairingVaroitus JIG for Checking BD Board Waveform IOPRecord Precedure Forced Reset Checks Prior to Parts Replacement and AdjustmentsREC/PLAY Retry Cause Display Mode PrecedureHexadecimal nBinary Conversion Table Location of Controls Section GeneralFront view Rear view Page Page Section Disassembly CaseFront Panel Seciton Main BoardMechanism Section MDM-5A Slider CAMBase Unit MBU-5A, BD Board SW BOARD, Loading Motor M103Setting the Test Mode Section Test ModePrecautions for USE of Test Mode Exiting the Test ModeSelecting the Test Mode Display Contents Mark GroupNon-Volatile Memory Mode EEP Mode Operating the Continuous Playback ModeMID Auto gain display Not used in servicing Test Mode DisplaysFunctions of Other Buttons Detrack check display Not used in servicingDisplay Contents When Lit When Off Meanings of Other DisplaysSection Electrical Adjustments Parts Replacement and AdjustmentPrecautions for Adjustments Precautions for Checking Laser Diode EmissinonPrecautions for USE of Optical PICK-UP KMS-260A Laser power meterCheck Prior to Repairs Temperature Compensation Offset CheckLaser Power Check Traverse CheckFocus Bias Check Play Checking MO Error Rate CheckCD Error Rate Check Self-Recording/playback CheckLaser Power Adjustment Initial Setting of Adjustment ValueTemperature Compensation Offset Adjutment Recording and Displaying the IOP InformationTraverse Adjustment Focus Bias Adjustment CD Auto Gain Control Output Level Adjustment Error Rate CheckAuto Gain Control Output Level Adjustment MO Auto Gain Control Output Level AdjustmentAdjusting Points and Connecting Points BD Board IC101 CXA2523AR RF AMP, FOCUS/TRACKING Error AMP Section DiagramsIC PIN Function Description Xrst SrdtSens SqsyMvci XrasXWE AsyoSprd SrdrSfdr SpfdMain Board IC100 CXD8607N A/D Converter TEST2 AvddlVDD1 LvddMain Board IC800 M30610MCA-264FP System Controller MDS-JB920 REC Analog Block Diagram Servo Section∙ Signal Path REC Digital∙ Signal Path Play Analog OUT Block Diagram Main SectionPlay Digital OUT Circuit Boards Location Printed Wiring Boards BD Section MDS-JB920 Schematic Diagram BD /2 See 53 for Waveforms. See page 70 and 71 for IC Block DiagramsWaveforms BD board Main board Disp board MDS-JB920 MDS-JB920 MDS-JB920 MDS-JB920 Other layers pattern Side a US, CND Schematic Diagram Panel Section See page 54 for Waveforms IC Block Diagrams BD Board IC101 Schematic Diagram BD Switch SectionPrinted Wiring Board BD Switch Section CXA2523ARIC121 CXD2654R IC152 BH6511FS-E2IC203 Main Board IC100 CXD8607NIC101 CXA8054M CXA8042ASIC200 CXD8767N SN74HC153ANS SN74HCU04ANS-E20Section Exploded Views Chassis SectionFront Panel Section Supplied with RV760204 205 206 201209 4-988-466-21 Spring ELECTROSTATIC, Leaf Base Unit Section MBU-5A Section Electrical Parts List Diode F1J6TP TANTAL. ChipDiode CXA2523ARDisp Main C252 Mylar CXA8042AS HZS6C1LHZ7.5CP-TK SN74HC153ANS390 LED SEL6210S-TH10 Standby Main PSWCoil with Core Vibrator LED SEL6810A-TH10 Mega Control TransistorSW VOL Sony Corporation
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