Sony MDS-JB920 Srdt, Sens, Xrst, Sqsy, Dqsy, Recp, Osci, Osco, Xtsl, Lrcki, Dvdd, Dvss, Xoe, Xcas

Page 33

•BD BOARD IC121 CXD2654R

(DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR, EFM/ACIRC ENCODER/DECODER, SHOCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER)

Pin No.

Pin Name

I/O

 

Function

 

 

 

 

 

 

 

 

1

MNT0 (FOK)

O

Focus OK signal output to the system controller (IC800)

 

“H” is output when focus is on (“L”: NG)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

MNT1 (SHOCK)

O

Track jump detection signal output to the system controller (IC800)

 

 

 

 

 

 

 

3

MNT2 (XBUSY)

O

Busy monitor signal output to the system controller (IC800)

 

 

 

 

 

 

 

4

MNT3 (SLOCK)

O

Spindle servo lock status monitor signal output to the system controller (IC800)

 

 

 

 

 

 

5

 

SWDT

I

Writing serial data signal input from the system controller (IC800)

 

 

 

 

 

 

6

 

SCLK

I (S)

Serial data transfer clock signal input from the system controller (IC800)

 

 

 

 

 

 

7

 

XLAT

I (S)

Serial data latch pulse signal input from the system controller (IC800)

 

 

 

 

 

 

8

 

SRDT

O (3)

Reading serial data signal output to the system controller (IC800)

 

 

 

 

 

 

9

 

SENS

O (3)

Internal status (SENSE) output to the system controller (IC800)

 

 

 

 

 

 

 

10

 

XRST

I (S)

Reset signal input from the system controller (IC800)

“L”: reset

 

 

 

 

 

 

11

 

SQSY

O

Subcode Q sync (SCOR) output to the system controller (IC800)

 

“L” is output every 13.3 msec

Almost all, “H” is output

 

 

 

 

 

 

 

 

 

 

 

 

 

12

 

DQSY

O

Digital In U-bit CD format subcode Q sync (SCOR) output to the system controller (IC800)

 

“L” is output every 13.3 msec

Almost all, “H” is output

 

 

 

 

 

 

 

 

 

 

 

 

 

13

 

RECP

I

Laser power selection signal input from the system controller (IC800)

 

“H”: recording mode, “L”: playback mode

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

14

 

XINT

O

Interrupt status output to the system controller (IC800)

 

 

 

 

 

 

 

15

 

TX

I

Recording data output enable signal input from the system controller (IC800)

 

Writing data transmission timing input (Also serves as the magnetic head on/off output)

 

 

 

 

 

 

 

 

 

 

16

 

OSCI

I

System clock signal (512Fs=22.5792 MHz) input from the D/A converter (IC200)

 

 

 

 

 

 

17

 

OSCO

O

System clock signal (512Fs=22.5792 MHz) output terminal

Not used (open)

 

 

 

 

 

 

 

 

18

 

XTSL

I

Input terminal for the system clock frequency setting

 

 

 

“L”: 45.1584 MHz, “H”: 22.5792 MHz (fixed at “H” in this set)

 

 

 

 

 

 

 

 

 

 

19

 

DIN0

I

Digital audio signal input terminal when recording mode (for digital optical in/digital coaxial in)

 

 

 

 

 

20

 

DIN1

I

Digital audio signal input terminal when recording mode Not used (fixed at “L”)

 

 

 

 

 

 

21

 

DOUT

O

Digital audio signal output terminal when playback mode (for digital optical out/digital coaxial

 

out)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

22

 

DATAI

I

Serial data input terminal Not used (fixed at “L”)

 

 

 

 

 

 

 

 

23

 

LRCKI

I

L/R sampling clock signal (44.1 kHz) input terminal

Not used (fixed at “L”)

 

 

 

 

 

 

24

 

XBCKI

I

Bit clock signal (2.8224 MHz) input terminal

Not used (fixed at “L”)

 

 

 

 

 

 

 

25

 

ADDT

I

Recording data input from the A/D converter (IC100)

 

 

 

 

 

 

 

 

 

26

 

DADT

O

Playback data output to the D/A converter (IC200)

 

 

 

 

 

 

 

 

27

 

LRCK

O

L/R sampling clock signal (44.1 kHz) output to the A/D converter (IC100) and D/A converter

 

(IC200)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

28

 

XBCK

O

Bit clock signal (2.8224 MHz) output to the A/D converter (IC100) and D/A converter (IC200)

 

 

 

 

 

 

29

 

FS256

O

Clock signal (11.2896 MHz) output terminal

Not used (open)

 

 

 

 

 

 

 

30

 

DVDD

—

Power supply terminal (+3.3V) (digital system)

 

 

 

 

 

 

 

 

 

31 to 34

A03 to A00

O

Address signal output to the D-RAM (IC124)

 

 

 

 

 

 

 

 

 

35

 

A10

O

Address signal output to the external D-RAM

Not used (open)

 

 

 

 

 

 

 

36 to 40

A04 to A08

O

Address signal output to the D-RAM (IC124)

 

 

 

 

 

 

 

 

 

41

 

A11

O

Address signal output to the external D-RAM

Not used (open)

 

 

 

 

 

 

 

 

 

42

 

DVSS

—

Ground terminal (digital system)

 

 

 

 

 

 

 

 

 

 

 

43

 

XOE

O

Output enable signal output to the D-RAM (IC124)

“L” active

 

 

 

 

 

 

 

44

 

XCAS

O

Column address strobe signal output to the D-RAM (IC124)

“L” active

 

 

 

 

 

 

 

 

 

 

* I (S) stands for schmitt input, I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O.

– 33 –

Page 32 Page 34
Image 33
Page 32 Page 34
Contents Specifications MDS-JE520MDM-5A General SELF-DIAGNOSIS FunctionItems of Error History Mode Items and Contents Table of Contents DiagramsSection Servicing Notes Flexible Circuit Board Repairing VarningVaroitus IOP JIG for Checking BD Board WaveformRecord Precedure Checks Prior to Parts Replacement and Adjustments Forced ResetREC/PLAY Precedure Retry Cause Display ModeHexadecimal nBinary Conversion Table Section General Location of ControlsFront view Rear view Page Page Case Section DisassemblyMain Board Front Panel SecitonSlider CAM Mechanism Section MDM-5ASW BOARD, Loading Motor M103 Base Unit MBU-5A, BD BoardPrecautions for USE of Test Mode Section Test ModeSetting the Test Mode Exiting the Test ModeDisplay Contents Mark Group Selecting the Test ModeOperating the Continuous Playback Mode Non-Volatile Memory Mode EEP ModeMID Functions of Other Buttons Test Mode DisplaysAuto gain display Not used in servicing Detrack check display Not used in servicingMeanings of Other Displays Display Contents When Lit When OffParts Replacement and Adjustment Section Electrical AdjustmentsPrecautions for USE of Optical PICK-UP KMS-260A Precautions for Checking Laser Diode EmissinonPrecautions for Adjustments Laser power meterLaser Power Check Temperature Compensation Offset CheckCheck Prior to Repairs Traverse CheckCD Error Rate Check Play Checking MO Error Rate CheckFocus Bias Check Self-Recording/playback CheckTemperature Compensation Offset Adjutment Initial Setting of Adjustment ValueLaser Power Adjustment Recording and Displaying the IOP InformationTraverse Adjustment Focus Bias Adjustment Auto Gain Control Output Level Adjustment Error Rate CheckCD Auto Gain Control Output Level Adjustment MO Auto Gain Control Output Level AdjustmentAdjusting Points and Connecting Points Section Diagrams BD Board IC101 CXA2523AR RF AMP, FOCUS/TRACKING Error AMPIC PIN Function Description Sens SrdtXrst SqsyXWE XrasMvci AsyoSfdr SrdrSprd SpfdMain Board IC100 CXD8607N A/D Converter VDD1 AvddlTEST2 LvddMain Board IC800 M30610MCA-264FP System Controller MDS-JB920 ∙ Signal Path Block Diagram Servo SectionREC Analog REC DigitalBlock Diagram Main Section ∙ Signal Path Play Analog OUTPlay Digital OUT Circuit Boards Location Printed Wiring Boards BD Section MDS-JB920 53 for Waveforms. See page 70 and 71 for IC Block Diagrams Schematic Diagram BD /2 SeeWaveforms BD board Main board Disp board MDS-JB920 MDS-JB920 MDS-JB920 MDS-JB920 Other layers pattern Side a US, CND Schematic Diagram Panel Section See page 54 for Waveforms Printed Wiring Board BD Switch Section Schematic Diagram BD Switch SectionIC Block Diagrams BD Board IC101 CXA2523ARIC152 BH6511FS-E2 IC121 CXD2654RIC101 CXA8054M Main Board IC100 CXD8607NIC203 CXA8042ASIC200 CXD8767N SN74HCU04ANS-E20 SN74HC153ANSChassis Section Section Exploded ViewsSupplied with RV760 Front Panel Section206 201 204 205209 4-988-466-21 Spring ELECTROSTATIC, Leaf Base Unit Section MBU-5A Section Electrical Parts List Diode TANTAL. ChipDiode F1J6TP CXA2523ARDisp Main C252 Mylar HZ7.5CP-TK HZS6C1LCXA8042AS SN74HC153ANS390 Coil with Core Vibrator Main PSWLED SEL6210S-TH10 Standby LED SEL6810A-TH10 Mega Control TransistorSW VOL Sony Corporation
Top Page Image Contents