Sony MDS-JB920 service manual Main Board IC100 CXD8607N A/D Converter

Page 36

•MAIN BOARD IC100 CXD8607N (A/D CONVERTER)

Pin No.

Pin Name

I/O

 

 

 

Function

 

 

 

 

 

 

 

 

1

 

INRP

I

R-ch analog signal (–) input terminal

 

 

 

 

 

 

 

 

 

 

2

 

INRM

I

R-ch analog signal (+) input terminal

 

 

 

 

 

 

 

 

3

 

REFI

I

Reference voltage (+3.3V) input terminal (for A/D converter section)

 

 

 

 

 

 

4

 

AVDD

—

Power supply terminal (+5V) (for A/D converter section, analog system)

 

 

 

 

 

 

5

 

AVSS

—

Ground terminal (for A/D converter section, analog system)

 

 

 

 

 

 

6

 

APD

I

Power down detection input of the A/D converter section (for analog section) “L”: power down

 

 

 

 

 

 

 

 

 

 

7

 

NU

—

Not used (open)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8

 

NU

—

Not used (open)

 

 

 

 

 

 

 

 

 

 

 

 

9

 

TEST1

I

Input terminal for the test (fixed at “L”)

 

 

 

 

 

 

 

 

10

 

LRCK1

I

L/R sampling clock signal (44.1 kHz) input from the CXD2654R (IC121) (for A/D converter

 

section)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

11

 

BCK1

I

Bit clock signal (2.8224 MHz) input from the CXD2654R (IC121) (for A/D converter section)

 

 

 

 

 

 

 

12

 

ADDT

O

Recording data output to the CXD2654R (IC121)

 

 

 

 

 

 

 

 

13

 

V35A

—

Power supply terminal (+3.3V) (for analog system)

 

 

 

 

 

 

 

14

 

VSS1

—

Ground terminal (for A/D converter section, digital system)

 

 

 

 

 

 

15

 

MCKI

I

Master clock (256Fs=11.2896 MHz) input of the A/D converter section

 

 

 

 

 

 

16

 

DPD

I

Reset signal input from the system controller (IC800) Reset signal is used as a detection signal

 

of power down to A/D converter section (digital section) “L”: reset (power down)

 

 

 

 

 

 

 

 

 

 

17

 

VSS2

—

Ground terminal (for D/A converter section, digital system)

 

 

 

 

 

 

 

18

 

RES

I

Reset signal input terminal

Reset signal is used as a initialize signal to D/A converter section

 

“L”: reset (initialize) Not used D/A converter section in this set

 

 

 

 

 

 

 

 

 

 

 

 

19

 

MODE

I

Writing data input terminal

Not used (fixed at “L”)

 

 

 

 

 

 

 

20

 

SHIFT

I

Serial clock signal input terminal

Not used (fixed at “L”)

 

 

 

 

21

XLATCH

I

Serial data latch pulse signal input terminal Not used (fixed at “L”)

 

 

 

 

 

 

22

 

256CK

O

256Fs (11.2896 MHz) clock signal output terminal

Not used (open)

 

 

 

 

 

 

23

 

V35D

—

Power supply terminal (+3.3V) (for digital system)

Not used (open)

 

 

 

 

 

24

 

VSS2

—

Ground terminal (for D/A converter section, digital system)

 

 

 

 

 

 

25

 

512FS

O

512Fs (22.5792 MHz) clock signal output terminal

Not used (pull down)

 

 

 

 

 

 

26

 

BCK2

I

Bit clock signal (2.8224 MHz) input terminal (for D/A converter section)

 

Not used (fixed at “L”)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

27

 

DADT

I

Playback data input terminal

Not used (fixed at “L”)

 

 

 

 

 

 

28

 

LRCK2

I

L/R sampling clock signal (44.1 kHz) input terminal (for D/A converter section)

 

Not used (fixed at “L”)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

29

 

VDD2

—

Power supply terminal (+5V) (for D/A converter section, digital system)

 

Not used (fixed at “L”)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

30

 

R1

O

R-ch PLM signal 1 output terminal

Not used (open)

 

 

 

 

 

 

31

AVDDR

—

Power supply terminal (+5V) (for R-ch side D/A converter section, analog system)

Not used (fixed at “L”)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

32

 

R2

O

R-ch PLM signal 2 output terminal

Not used (open)

 

 

 

 

 

33

 

AVSSR

—

Ground terminal (for R-ch side D/A converter section, analog system)

 

 

 

 

 

34

 

XVDD

—

Power supply terminal (+5V) (for X’tal system) Not used (open)

 

 

 

 

 

 

35

 

XOUT

O

System clock output terminal (22 MHz)

Not used (open)

 

 

 

 

 

 

36

 

XIN

I

System clock input terminal (22 MHz)

Not used (fixed at “L”)

 

 

 

 

 

 

 

 

37

 

XVSS

—

Ground terminal (for X’tal system)

 

 

 

 

 

 

 

 

38

 

AVSSL

—

Ground terminal (for L-ch side D/A converter section, analog system)

 

 

 

 

 

 

39

 

L2

O

L-ch PLM signal 2 output terminal

Not used (open)

 

 

 

 

 

 

 

 

 

 

– 36 –

Page 35 Page 37
Image 36
Page 35 Page 37
Contents Specifications MDS-JE520MDM-5A SELF-DIAGNOSIS Function GeneralItems of Error History Mode Items and Contents Table of Contents DiagramsSection Servicing Notes Flexible Circuit Board Repairing VarningVaroitus JIG for Checking BD Board Waveform IOPRecord Precedure Checks Prior to Parts Replacement and Adjustments Forced ResetREC/PLAY Retry Cause Display Mode PrecedureHexadecimal nBinary Conversion Table Section General Location of ControlsFront view Rear view Page Page Section Disassembly CaseFront Panel Seciton Main BoardMechanism Section MDM-5A Slider CAMBase Unit MBU-5A, BD Board SW BOARD, Loading Motor M103Section Test Mode Precautions for USE of Test ModeSetting the Test Mode Exiting the Test ModeSelecting the Test Mode Display Contents Mark GroupOperating the Continuous Playback Mode Non-Volatile Memory Mode EEP ModeMID Test Mode Displays Functions of Other ButtonsAuto gain display Not used in servicing Detrack check display Not used in servicingDisplay Contents When Lit When Off Meanings of Other DisplaysSection Electrical Adjustments Parts Replacement and AdjustmentPrecautions for Checking Laser Diode Emissinon Precautions for USE of Optical PICK-UP KMS-260APrecautions for Adjustments Laser power meterTemperature Compensation Offset Check Laser Power CheckCheck Prior to Repairs Traverse CheckPlay Checking MO Error Rate Check CD Error Rate CheckFocus Bias Check Self-Recording/playback CheckInitial Setting of Adjustment Value Temperature Compensation Offset AdjutmentLaser Power Adjustment Recording and Displaying the IOP InformationTraverse Adjustment Focus Bias Adjustment Error Rate Check Auto Gain Control Output Level AdjustmentCD Auto Gain Control Output Level Adjustment MO Auto Gain Control Output Level AdjustmentAdjusting Points and Connecting Points Section Diagrams BD Board IC101 CXA2523AR RF AMP, FOCUS/TRACKING Error AMPIC PIN Function Description Srdt SensXrst SqsyXras XWEMvci AsyoSrdr SfdrSprd SpfdMain Board IC100 CXD8607N A/D Converter Avddl VDD1TEST2 LvddMain Board IC800 M30610MCA-264FP System Controller MDS-JB920 Block Diagram Servo Section ∙ Signal PathREC Analog REC DigitalBlock Diagram Main Section ∙ Signal Path Play Analog OUTPlay Digital OUT Circuit Boards Location Printed Wiring Boards BD Section MDS-JB920 Schematic Diagram BD /2 See 53 for Waveforms. See page 70 and 71 for IC Block DiagramsWaveforms BD board Main board Disp board MDS-JB920 MDS-JB920 MDS-JB920 MDS-JB920 Other layers pattern Side a US, CND Schematic Diagram Panel Section See page 54 for Waveforms Schematic Diagram BD Switch Section Printed Wiring Board BD Switch SectionIC Block Diagrams BD Board IC101 CXA2523ARIC121 CXD2654R IC152 BH6511FS-E2Main Board IC100 CXD8607N IC101 CXA8054MIC203 CXA8042ASIC200 CXD8767N SN74HC153ANS SN74HCU04ANS-E20Section Exploded Views Chassis SectionFront Panel Section Supplied with RV760206 201 204 205209 4-988-466-21 Spring ELECTROSTATIC, Leaf Base Unit Section MBU-5A Section Electrical Parts List TANTAL. Chip DiodeDiode F1J6TP CXA2523ARDisp Main C252 Mylar HZS6C1L HZ7.5CP-TKCXA8042AS SN74HC153ANS390 Main PSW Coil with Core VibratorLED SEL6210S-TH10 Standby LED SEL6810A-TH10 Mega Control TransistorSW VOL Sony Corporation
Top Page Image Contents