XR-M510
Pin No. | Pin Name | I/O |
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77 |
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| I | Battery detection signal input from the SONY bus interface (IC501) and battery detect circuit | |||||||
| “L” is input at low voltage |
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78 |
| NC | O | Not used (open) |
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79 |
| KEYACK | I | Input of acknowledge signal for the key entry Acknowledge signal is input to accept function | |||||||
| and eject keys in the power off status | On at input of “H” |
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80 |
| AD ON |
| A/D converter power control signal output terminal |
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| O | When the KEYACK (pin ul) that controls reference voltage power for key A/D conversion input | |||||||||
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| is active, “L” is output from this terminal to enable the input |
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81 |
| ACCIN | I | Accessory detection signal input terminal “L”: accessory on |
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82 | FLS PWON | O | Power on/off control signal output of the illumination LED and liquid crystal display driver | ||||||||
(IC901, 902) “H”: power on |
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83 |
| O | Main system power supply on/off control signal output terminal | “H”: power on | |||||||
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84 |
| TESTIN | I | Setting terminal for the test mode | “L”: test mode, Normally: fixed at “H” | ||||||
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85 |
| RAMBU | I | Internal RAM reset detection signal input from the RN5VD33AA (IC603) | |||||||
| Input terminal to check that RAM data are not destroyed due to low voltage | ||||||||||
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| This checking is made within 100 msec after reset |
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86 |
| HSTX | I | Hardware standby input terminal | “L”: hardware standby mode | Reset signal input in this set | |||||
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87 |
| MD2 | I | Setting terminal for the CPU operational mode (fixed at “L” in this set) | |||||||
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88 |
| MD1 | I | Setting terminal for the CPU operational mode (fixed at “H” in this set) | |||||||
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89 |
| MD0 | I | Setting terminal for the CPU operational mode (fixed at “H” in this set) | |||||||
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90 |
| RST | I | System reset signal input from the reset signal generator (IC602) and reset switch (S901, 902) | |||||||
| “L”: reset “L” is input for several 100 msec after power on, then it changes to “H” | ||||||||||
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91 |
| VSS | — | Ground terminal |
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92 |
| X0 | I | Main system clock input terminal (3.68 MHz) |
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93 |
| X1 | O | Main system clock output terminal (3.68 MHz) |
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94 |
| VCC | — | Power supply terminal (+5V) |
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95 |
| ILLIN | I | Auto dimmer control illumination line detection signal input terminal | |||||||
| “L” is input at dimmer detection |
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96 |
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| Detection signal input from the motor overload detection circuit for the front panel open/close | |||||||
| I | motor (M601) |
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| “L” is input when the motor current exceeds the specified value |
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97 |
| MOT– | O | Front panel open/close motor (M601) drive signal (in panel close direction) output to the | |||||||
| BA6288FS (IC502) | “H” active | *2 |
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98 |
| MOT+ | O | Front panel open/close motor (M601) drive signal (in panel open direction) output to the | |||||||
| BA6288FS (IC502) | “H” active | *2 |
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99 | CLOSE SW | I | Front panel open/close detect switch input terminal | “L” is input when the front panel is closed | |||||||
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100 | OPEN SW | I | Front panel open/close detect switch input terminal | “L” is input when the front panel is opened | |||||||
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101 to 103 |
| NC | I | Not used (fixed at “H”) |
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104, 105 | DSTSEL1, | I | Destination setting terminal (A/D input) | *3 |
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| DSTSEL2 |
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106 |
| BOOT | O | Serial data output to the liquid crystal display drive controller (IC607) | |||||||
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107 | DSP GAIN | O | Not used (open) |
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108 |
| DSP ON | O | Power supply on/off control signal output terminal | “H”: DSP on | Not used (open) | |||||
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109 |
| NC | O | Not used (open) |
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110 |
| I | Emphasis control signal input terminal | Not used (fixed at “L”) |
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111 | PACK SW | I | Cassette in/out detect switch (S901) | “L”: cassette in |
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112 |
| 4V SEL | I | Input terminal of whether line driver is mounted or not is detected | |||||||
| “H”: line driver is not mounted |
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113 |
| P SEL | I | Power select input terminal Not used (fixed at “L”) |
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40