Sony MDS-JE640 specifications MNT0 FOK

Page 49

• IC151 CXD2662R Digital Signal Processor, Digital Servo Signal Processor (BD BOARD)

Pin No.

Pin Name

I/O

 

 

 

 

Function

 

 

 

 

 

 

 

 

1

MNT0 (FOK)

O

 

FOK signal output to the system control (monitor output)

 

“H” is output when focus is on

 

 

 

 

 

 

 

 

 

 

 

 

2

MNT1 (SHCK)

O

 

Track jump detection signal output to the system control (monitor output)

 

 

 

 

 

 

 

 

3

MNT2 (XBUSY)

O

 

Monitor 2 output to the system control (monitor output)

 

 

 

 

 

 

 

 

4

MNT3 (SLOC)

O

 

Monitor 3 output to the system control (monitor output)

 

 

 

 

 

 

 

 

5

SWDT

I

 

Writing data signal input from the system control

 

 

 

 

 

 

 

 

6

SCLK

I (S)

 

Serial clock signal input from the system control

 

 

 

 

 

 

 

 

7

XLAT

I (S)

 

Serial latch signal input from the system control

 

 

 

 

 

 

 

 

8

SRDT

O (3)

 

Reading data signal output to the system control

 

 

 

 

 

 

 

 

9

SENS

O (3)

 

Internal status (SENSE) output to the system control

 

 

 

 

 

 

 

 

10

XRST

I (S)

 

Reset signal input from the system control “L”: Reset

 

 

 

 

 

 

 

 

11

SQSY

O

 

Subcode Q sync (SCOR) output to the system control

 

“L” is output every 13.3 msec. Almost all, “H” is output

 

 

 

 

 

 

 

 

 

 

 

 

12

DQSY

O

 

Digital In U-bit CD format or MD format subcode Q sync (SCOR) output to the system

 

control

 

 

 

 

 

 

 

 

 

 

 

 

13

RECP

I

 

Laser power switching input from the system control “H”: Recording, “L”: Playback

 

 

 

 

 

 

 

 

14

XINT

O

 

Interrupt status output to the system control

 

 

 

 

 

 

 

 

15

TX

I

 

Recording data output enable input from the system control

 

 

 

 

 

 

 

 

16

OSCI

I

 

System clock input (512Fs=22.5792 MHz)

 

 

 

 

 

 

 

 

17

OSCO

O

 

System clock output (512Fs=22.5792 MHz) (Not used)

 

 

 

 

 

 

 

 

18

XTSL

I

 

System clock frequency setting “L”: 45.1584 MHz, “H”: 22.5792 MHz (Fixed at “H”)

 

 

 

 

 

 

 

 

19

DIN0

I

 

Digital audio input (Optical input)

 

 

 

 

 

 

 

 

20

DIN1

I

 

Digital audio input (Optical input)

 

 

 

 

 

 

 

 

21

DOUT

O

 

Digital audio output (Optical output)

 

 

 

 

 

 

 

 

22

DADTI

I

 

Serial data input

23

LRCKI

I

 

LR clock input “H” : Lch, “L” : R ch

 

 

 

 

 

 

 

 

24

XBCKI

I

 

Serial data clock input

 

 

 

 

 

25

ADDT

I

 

Data input from the A/D converter

 

 

 

 

 

 

 

 

26

DADT

O

 

Data output to the D/A converter

 

 

 

 

 

 

 

 

27

LRCK

O

 

LR clock output for the A/D and D/A converter (44.1 kHz)

 

 

 

 

 

 

 

 

28

XBCK

O

 

Bit clock output to the A/D and D/A converter (2.8224 MHz)

 

 

 

 

 

 

 

 

29

FS256

O

 

11.2896 MHz clock output (Not used)

 

 

 

 

 

30

DVDD

 

+3V power supply (Digital)

 

 

 

 

 

31 to 34

A03 to A00

O

 

DRAM address output

35

A10

O

 

DRAM address output (Not used)

 

 

 

 

 

 

 

 

36 to 40

A04 to A08

O

 

DRAM address output

 

 

 

 

 

 

 

 

41

A11

O

 

DRAM address output (Not used)

 

 

 

 

 

 

 

 

42

DVSS

 

Ground (Digital)

43

XOE

O

 

Output enable output for DRAM

 

 

 

 

 

 

 

44

XCAS

O

 

CAS signal output for DRAM

45

A09

O

 

Address output for DRAM

 

 

 

 

 

 

 

 

46

XRAS

O

 

 

 

 

signal output for DRAM

 

RAS

 

 

 

 

 

47

XWE

O

 

Write enable signal output for DRAM

 

 

 

 

 

 

 

 

* I (S) stands for Schmidt input, I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O

49

Image 49
Contents Inputs SpecificationsOutputs NEWSELF-DIAGNOSIS Function Supplied accessoriesGeneral Three- or five Digit code Cause/Remedy MessageItems of Error History Mode Items and Contents Disassembly Table of ContentsDiagrams Exploded ViewsFlexible Circuit Board Repairing Section Service NotesIOP JIG for Checking BD Board WaveformRecord Precedure Forced Reset Checks Prior to Parts Replacement and AdjustmentsMain Board Component Side Bit Binary Retry Cause Display ModeHexadecimal t Binary Conversion Table Section General Front Panel Section Section DisassemblyPT BOARD, VOL-SEL Board Main BoardBD Board Mechanism Deck Section MDM-7APrecautions for USE of Test Mode Section Test ModeSetting the Test Mode Exiting the Test ModeDisplay Details Mark Group Selecting the Test ModeMENU/NO Operating the Continuous Playback ModeMode display Test Mode DisplaysError rate display Functions of Other ButtonsMeanings of Other Displays When Memory NG is DisplayedAutomatic SELF-DIAGNOSIS Function InformationParts Replacement and Adjustment Section Electrical AdjustmentsCheck before replacement YES Adjustment flowPrecautions for USE of Optical PICK- UP KMS-260B Precautions for Checking Laser Diode EmissionPrecautions for Adjustments Checks Prior to Repairs Using the Continuously Recorded DiscOther Checks Auto CheckCD Error Rate Check Play Check MO Error Rate CheckTemperature Compensation Offset Adjutment Initial Setting of Adjustment ValueLaser Power Adjustment Iop NV Save Traverse AdjustmentYES Focus Bias AdjustmentAuto Gain Control Output Level Adjustment Error Rate CheckCD Auto Gain Control Output Level Adjustment MO Auto Gain Control Output Level AdjustmentAdjusting Points and Connecting Points For schematic diagrams Section DiagramsFor printed wiring boards Circuit Boards LocationSignal Path Block Diagrams BD SectionMDS-JE640 REC Analog Main SectionMain Board BD BoardDisplay Board Semiconductor Printed Wiring Board BD SectionPIN PIN Function Printed Wiring Board Main Section Side a IC1 Printed Wiring Board Main Section Side BIC2 PIN MDS-JE640 Schematic Diagram Main /3 See page 47 for IC Block Diagrams Printed Wiring Board Power Section Printed Wiring Board Display Section Schematic Diagram Display Section See page 34 for Waveforms IC101 CXA2523AR BD Board IC Block DiagramsIC400 LA5643 Main Board IC101 CXA2523AR RF Amplifier BD Board IC PIN FunctionsMNT0 FOK Mvci Tfdr IC1 M30805SGP System Control Main Board HLDA/ALE Chassis Section Section Exploded ViewsPanel ASSY, Front Silver Panel ASSY, Front Black AEP,UK,CIS,SP,MY202 220 201 213 215 216 205 218 207 Mechanism MDM-7AMotor ASSY, Spindle HEAD, Over LightMotor ASSY, Sled Motor ASSY, LoadingSection Electrical Parts List Metal Chip IC TC7WU04FUTE12RIC MC74ACT08DTR2 IC BA033FP-E2Display KEY-SW Main CONNECTOR, FFC 17P PIN, Connector 3PPIN, Connector 4P PLUG, Connector 10P DiodeAEP,UK,CIS IC SN74LVU04ANSRTransistor UN2211-TX Transistor UN2111-TXTRANSFORMER, Power CND ConnectorTRANSFORMER, Power SP,MY Composition Circuit BlockVOL-SEL Sony Corporation