Sony MDS-JE640 specifications Mvci

Page 50

Pin No.

Pin Name

I/O

Function

 

 

 

 

48

D1

I/O

 

 

 

 

 

49

D0

I/O

Data input/output for DRAM

 

 

 

 

50, 51

D2, D3

I/O

 

 

 

 

 

52

MVCI

I (S)

Clock input from an external VCO (Fixed at “L”)

 

 

 

 

53

ASYO

O

Playback EFM duplex signal output

 

 

 

 

54

ASYI

I (A)

Playback EFM comparator slice level input

 

 

 

 

55

AVDD

—

+3V power supply (Analog)

 

 

 

 

56

BIAS

I (A)

Playback EFM comparator bias current input

 

 

 

 

57

RFI

I (A)

Playback EFM RF signal input

 

 

 

 

58

AVSS

—

Ground (Analog)

 

 

 

 

59

PCO

O (3)

Phase comparison output for the recording/playback EFM master PLL

 

 

 

 

60

FILI

I (A)

Filter input for the recording/playback EFM master PLL

 

 

 

 

61

FILO

O (A)

Filter output for the recording/playback EFM master PLL

 

 

 

 

62

CLTV

I (A)

Internal VCO control voltage input for the recording/playback EFM master PLL

 

 

 

 

63

PEAK

I (A)

Light amount signal peak hold input from the CXA2523AR

 

 

 

 

64

BOTM

I (A)

Light amount signal bottom hold input from the CXA2523AR

 

 

 

 

65

ABCD

I (A)

Light amount signal input from the CXA2523AR

 

 

 

 

66

FE

I (A)

Focus error signal input from the CXA2523AR

 

 

 

 

67

AUX1

I (A)

Auxiliary A/D input

 

 

 

 

68

VC

I (A)

Middle point voltage (+1.5V) input from the CXA2523AR

 

 

 

 

69

ADIO

O (A)

Monitor output of the A/D converter input signal (Not used)

 

 

 

 

70

AVDD

—

+3V power supply (Analog)

 

 

 

 

71

ADRT

I (A)

A/D converter operational range upper limit voltage input (Fixed at “H”)

 

 

 

 

72

ADRB

I (A)

A/D converter operational range lower limit voltage input (Fixed at “L”)

 

 

 

 

73

AVSS

—

Ground (Analog)

 

 

 

 

74

SE

I (A)

Sled error signal input from the CXA2523AR

 

 

 

 

75

TE

I (A)

Tracking error signal input from the CXA2523AR

 

 

 

 

76

DCHG

I (A)

Connected to +3V power supply

 

 

 

 

77

APC

I (A)

Error signal input for the laser digital APC (Fixed at “L”)

 

 

 

 

78

ADFG

I (S)

ADIP duplex FM signal input from the CXA2523AR (22.05 ± 1 kHz)

 

 

 

 

79

F0CNT

O

Filter f0 control output to the CXA2523AR

 

 

 

 

80

XLRF

O

Control latch output to the CXA2523AR

 

 

 

 

81

CKRF

O

Control clock output to the CXA2523AR

 

 

 

 

82

DTRF

O

Control data output to the CXA2523AR

 

 

 

 

83

APCREF

O

Reference PWM output for the laser APC

 

 

 

 

84

TEST0

O

PWM output for the laser digital APC (Not used)

 

 

 

 

85

TRDR

O

Tracking servo drive PWM output (–)

 

 

 

 

•Abbreviation

EFM: Eight to Fourteen Modulation

PLL : Phase Locked Loop

VCO: Voltage Controlled Oscillator

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Contents Outputs SpecificationsInputs NEWGeneral Supplied accessoriesSELF-DIAGNOSIS Function Three- or five Digit code Cause/Remedy MessageItems of Error History Mode Items and Contents Diagrams Table of ContentsDisassembly Exploded ViewsSection Service Notes Flexible Circuit Board RepairingJIG for Checking BD Board Waveform IOPRecord Precedure Main Board Component Side Checks Prior to Parts Replacement and AdjustmentsForced Reset Retry Cause Display Mode Bit BinaryHexadecimal t Binary Conversion Table Section General Section Disassembly Front Panel SectionMain Board PT BOARD, VOL-SEL BoardMechanism Deck Section MDM-7A BD BoardSetting the Test Mode Section Test ModePrecautions for USE of Test Mode Exiting the Test ModeSelecting the Test Mode Display Details Mark GroupOperating the Continuous Playback Mode MENU/NOError rate display Test Mode DisplaysMode display Functions of Other ButtonsAutomatic SELF-DIAGNOSIS Function When Memory NG is DisplayedMeanings of Other Displays InformationCheck before replacement Section Electrical AdjustmentsParts Replacement and Adjustment Adjustment flow YESPrecautions for Adjustments Precautions for Checking Laser Diode EmissionPrecautions for USE of Optical PICK- UP KMS-260B Using the Continuously Recorded Disc Checks Prior to RepairsAuto Check Other ChecksPlay Check MO Error Rate Check CD Error Rate CheckLaser Power Adjustment Initial Setting of Adjustment ValueTemperature Compensation Offset Adjutment Traverse Adjustment Iop NV SaveFocus Bias Adjustment YESCD Auto Gain Control Output Level Adjustment Error Rate CheckAuto Gain Control Output Level Adjustment MO Auto Gain Control Output Level AdjustmentAdjusting Points and Connecting Points For printed wiring boards Section DiagramsFor schematic diagrams Circuit Boards LocationMDS-JE640 Block Diagrams BD SectionSignal Path Main Section REC AnalogDisplay Board BD BoardMain Board Printed Wiring Board BD Section SemiconductorPIN PIN Function Printed Wiring Board Main Section Side a IC2 Printed Wiring Board Main Section Side BIC1 PIN MDS-JE640 Schematic Diagram Main /3 See page 47 for IC Block Diagrams Printed Wiring Board Power Section Printed Wiring Board Display Section Schematic Diagram Display Section See page 34 for Waveforms IC Block Diagrams IC101 CXA2523AR BD BoardIC400 LA5643 Main Board IC PIN Functions IC101 CXA2523AR RF Amplifier BD BoardMNT0 FOK Mvci Tfdr IC1 M30805SGP System Control Main Board HLDA/ALE Section Exploded Views Chassis SectionPanel ASSY, Front Black AEP,UK,CIS,SP,MY Panel ASSY, Front SilverMechanism MDM-7A 202 220 201 213 215 216 205 218 207Motor ASSY, Sled HEAD, Over LightMotor ASSY, Spindle Motor ASSY, LoadingSection Electrical Parts List IC MC74ACT08DTR2 IC TC7WU04FUTE12RMetal Chip IC BA033FP-E2Display KEY-SW Main PIN, Connector 4P PIN, Connector 3PCONNECTOR, FFC 17P PLUG, Connector 10P DiodeTransistor UN2211-TX IC SN74LVU04ANSRAEP,UK,CIS Transistor UN2111-TXTRANSFORMER, Power SP,MY ConnectorTRANSFORMER, Power CND Composition Circuit BlockVOL-SEL Sony Corporation
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