Texas Instruments TMS320C645x manual TX Operation, Write Transactions

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SRIO Functional Description

Figure 13. Load/Store Module Data Flow

UDI	Peripheral

I/O pins

RapidIO and

Port

FIFO

TX

FIFO

RX

FIFO

Load/store

MMR
LSU1	LSU2	LSU3	LSU4

Control
and
arbitrator	Shared
	Shared
	TX
	data
Response
timer	Shared
	Shared
	RX
	data

Write descriptors

Config access

DMA

request

DMA

response

CPU

L2

=

2.3.3.2TX Operation

WRITE Transactions:

The TX buffers are implemented in a single SRAM and shared between multiple cores. A state machine arbitrates and assigns available buffers between the LSUs. When the DMA bus read request is transmitted, the appropriate TX buffer address is specified within it. The data payload is written to that buffer through the DMA bus response transaction. Depending on the architecture of the device, interleaving of multi-segmented DMA bus responses from the DMA is possible. Upon receipt of a DMA bus read response segment, the unit checks the completion status of the payload. Note that only one payload can be completed in any single DMA bus cycle. The Load/Store module can only forward the packet to the TX FIFO after the final payload byte from the DMA bus response has been written into the shared memory buffer. Once the packet is forwarded to the TX FIFO, the shared buffer can be released and made available for a new transaction.

The TX buffer space is dynamically shared among all outgoing sources, including the Load/Store Unit (LSU) and the TX CPPI, as well as the response packets from RX CPPI and the Memory Access Unit (MAU). Thus, the buffer space memory must be partitioned to handle packets with and without payloads. A 4.5KB buffer space is configured to support 16 packets with payloads up to 256B, in addition to 16 packets without payloads. The SRAM is configured as a 128-bit wide two port, which matches the UDI width of the TX FIFOs.

Data leaves the shared buffer pool sequentially in order of receipt, not based on the packet priority. However, if fabric congestion occurs, priority can affect the order in which the data leaves the TX FIFOs. A reordering mechanism exists here, which transmits the highest priority packets first if RETRY acknowledges.

SPRU976 –March 2006

Serial RapidIO (SRIO)

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Contents Users Guide Submit Documentation Feedback Contents Errrstevnticrr Base Device ID CSR Baseid List of Figures Load/Store Module Interrupt Condition Routing Registers 150 Port Error Rate Threshold CSR n SP n Errthresh List of Tables LSUn Control Register 0 LSUnREG0 Field Descriptions Base Device ID CSR Baseid Field Descriptions Read This First RapidIO Architectural Hierarchy General RapidIO SystemOverview 3 1x/4x LP-Serial RapidIO Interconnect ArchitectureFeatures Supported in Srio RapidIO Feature Support in SrioStandards Features Not SupportedExternal Devices Requirements RapidIO Documents and LinksPeripheral Data Flow OverviewOperation Sequence Srio PacketsExample Packet Streaming Write Operation Sequence4x RapidIO Packet Data Stream Streaming-Write Class Control SymbolsPacket Type Srio Packet Ftype/TtypeFtype Ttype Packet Type Block Diagram Srio PinsFunctional Operation Pin DescriptionSrio Conceptual Block Diagram Enabling the PLL Serdes and its ConfigurationsBits of Serdescfg nCNTL Register 0x120 0x12c Bit Name Value DescriptionLine Rate versus PLL Output Clock Frequency Bits of Serdescfg nCNTL Register 0x120 0x12cRate Bit Effects Enabling the Receiver Frequency Range versus MPYBits of Serdescfgrx nCNTL Registers Bits of SERDESCFGRXnCNTL Registers Disabled. Loss of signal detection disabledBit Field Value Description 1514 Enabling the Transmitter EQ BitsBits of Serdescfgtx nCNTL Registers CFGRX2219 Low Freq GainSwing Bits Bits of Serdescfgtx nCNTL RegistersDE Bits DirectIO Serdes Configuration ExampleRapidIO Packet Header Field Control/Command Register Field MappingStatus Fields Control/Command Register RapidIO Packet Header FieldStatus Field Function BSYLSU Registers Timing Detailed Data Path Description Example Burst NwriterWrite Transactions TX OperationRead Transactions RX Operation SegmentationMessage Passing Reset and Power Down StateCppi RX Scheme for RapidIO Queue Mapping Table Address Offset 0x0800 0x08FC Bit Name Description Queue Mapping Register Rxumapl nRX Buffer Descriptor Fields Field Description RX Buffer Descriptor Field DescriptionsField Description RX Buffer Descriptor Field DescriptionsRX Cppi Mode Explanation Cppi Boundary Diagram TX Buffer Descriptor Field Definitions TX Buffer Descriptor FieldsUses this bit to reclaim buffers Ssize TXQUEUECNTL0- Address Offset 0x7E0 Name Bit Access Reset Value DescriptionTXQUEUECNTL1- Address Offset 0x7E4 TXQUEUECNTL2- Address Offset 0x7E8TXQueueMap10 2316 0x0A Detailed Data Path Description RX Operation Message Passing Software RequirementsTX Operation Queue Mapping Initialization ExampleRX Buffer Descriptor NDP TX Buffer DescriptorStart Message Passing MaintenanceDoorbell Operation DoorbellDetailed Description Congestion ControlName Bit Transmit Source Flow Control Masks Endianness Configuration Bus ExampleDMA Example ResetEnable and Enable Status Registers Reset SummaryBLK8ENSTA BLK7ENSTA Enstat Enable and Enable Status Bit Field DescriptionsGblen BLK0ENBLK1ENSTAT BLK1ENBLK2EN BLK2ENSTATEmulation Software Shutdown DetailsBLK8ENSTAT Peren Soft FreeEnabling the Srio Peripherals Emulation Control SignalsPeren Peripheral Initializations 11.2 PLL, Ports, Device ID and Data Rate InitializationsSet Device ID Registers Read register to check portx1-4 OK bit Assert the Peren bit to enable logical layer data flowConfiguration Bootload CapabilityBootload Data Movement Device WakeupERR MSG REQGeneral Description CPU InterruptsInterrupt Condition Control Registers Interrupt Source Configuration Options Where ICS0 Doorbell1, bit 0, through ICS15 Doorbell1, bit Interrupt Conditions LSU Interrupt Condition Clear Registers Iccr Address Offset ICS2 ICS1 ICS0 ICS11 ICS10 ICS9 ICS8ICC11 ICC10 ICC9 ICC8 ICC2 ICC1 ICC0DOORBELL0ICRR2 Address Offset Interrupt Condition Routing OptionsLSUICRR2 Address Offset 0x02E8 LSUICRR1 Address Offset 0x02E4LSUICRR3 Address Offset 0x02EC ERRRSTEVNTICRR2 Address Offset 0x02F4 Interrupt Status Decode RegistersERRRSTEVNTICRR3 Address Offset 0x02F8 ICR2 ICR1 ICR0Sharing of Isdr Bits Interrupt Pacing Interrupt GenerationISDR3 ISDR2 ISDR1 ISDR9 ISDR8 ISDR7 ISDR6 ISDR5 ISDR4 ISDR0 INTDSTnRATECNTL Interrupt Rate Control Register Interrupt HandlingInterrupt Conditions Serial Rapid IO Srio Registers IntroductionOffset Acronym Register Description Offset Acronym Register Description Serial Rapid IO Srio RegistersErrrstevntic LSUICRR3RR2 RR3LSU3REG1 QUEUE2TXDMAC QUEUE1TXDMACQUEUE3TXDMAC QUEUE4TXDMACQUEUE12RXDMA SKS6 TxcppiflowmaSKS7 RxqueuetearRXUMAPH18 RXUMAPL18RXUMAPL19 RXUMAPH19Asblyinfo AsblyidPefeat SrcopPTDBG0 SP0ERRATTRCASP0ERRCAPTDB SP0ERRRATESP3ERRRATE TimerSP3ERRTHRESH SpipdiscoveryPeripheral ID Register PID Field Descriptions Peripheral Identification Register PIDType Class REVPeripheral Control Register PCR Field Descriptions Peripheral Control Register PCRPere Soft Free Bit FieldPeripheral Settings Control Register Persetcntl 1XMODE CbatransprPrescalerse LectENPLL2 ENPLL3ENPLL1 Peripheral Global Enable Register Gblen Field Descriptions Peripheral Global Enable Register GblenGBL Peripheral Global Enable Status Register GblenstatENS TATBlock n Enable Register BLKnEN Field Descriptions Block n Enable Register BLKnENBlock n Enable Status Register BLKnENSTAT Block n Enable Status Register BLKnENSTATRapidIO DEVICEID1 Register DEVICEIDREG1 Field Descriptions RapidIO DEVICEID1 Register DEVICEIDREG18BNODEID 16BNODEIDRapidIO DEVICEID2 Register DEVICEIDREG2 Field Descriptions RapidIO DEVICEID2 Register DEVICEIDREG2Packet Forwarding Register n for 16b DeviceIDs PF16BCNTLn Packet Forwarding Register n for 8b DeviceIDs PF8BCNTLn Term Invpa Rate Buswidth CDR LOS AlignCFGRX2219 Low Freq Gain Zero Freq at e28 min Swing Invpa Rate Buswidth EnftEntx DE Bits Swing BitsCFGTX119 Amplitude mV dfpp CFGTX1512 Amplitude ReductionMPY Enpll Serdes Macro Configuration Register n SERDESCFGnCNTLRIOCLK/RIOCLK MPYDOORBELLn Interrupt Status Register DOORBELLnICSR DOORBELLn Interrupt Status Register DOORBELLnICSRDOORBELLn Interrupt Clear Register DOORBELLnICCR DOORBELLn Interrupt Clear Register DOORBELLnICCRRX Cppi Interrupt Status Register Rxcppiicsr RX Cppi Interrupt Status Register RxcppiicsrRX Cppi Interrupt Clear Register Rxcppiiccr RX Cppi Interrupt Clear Register RxcppiiccrTX Cppi Interrupt Status Register Txcppiicsr TX Cppi Interrupt Status Register TxcppiicsrTX Cppi Interrupt Clear Register Txcppiiccr TX Cppi Interrupt Clear Register TxcppiiccrLSU Status Interrupt Register Lsuicsr Field Descriptions LSU Status Interrupt Register LsuicsrICS31-0 Load/Store module interrupt condition status bits LSU Clear Interrupt Register LSU Iccr Field Descriptions LSU Clear Interrupt Register LSU IccrICS31-0 Load/Store module interrupt clear bits 31-17 126 DOORBELLn Interrupt Condition Routing Register DOORBELLnICRR 128 ICR RX Cppi Interrupt condition routing bits RX Cppi Interrupt Condition Routing Register Rxcppi IcrrRX Cppi Interrupt Condition Routing Register Rxcppi ICRR2 RX Cppi Interrupt Condition Routing Register Rxcppi ICRR2ICR TX Cppi Interrupt condition routing bits TX Cppi Interrupt Condition Routing Register Txcppi IcrrTX Cppi Interrupt Condition Routing Register Txcppi ICRR2 TX Cppi Interrupt Condition Routing Register Txcppi ICRR2ICR LSU Module Interrupt Condition Routing Register 0 LSUICRR0LSU Module Interrupt Condition Routing Register 1 LSUICRR1 LSU Module Interrupt Condition Routing Register 1 LSUICRR1LSU Module Interrupt Condition Routing Register 2 LSUICRR2 LSU Module Interrupt Condition Routing Register 2 LSUICRR2LSU Module Interrupt Condition Routing Register 3 LSUICRR3 LSU Module Interrupt Condition Routing Register 3 LSUICRR3Errrstevnticrr Field Descriptions ErrrstevnticrrICR11 ERRRSTEVNTICRR2 Field DescriptionsERRRSTEVNTICRR3 Field Descriptions ERRRSTEVNTICRR3INTDSTn Interrupt Status Decode Registers INTDSTnDECODE INTDSTn Interrupt Status Decode Registers INTDSTnDECODECountdownvalue INTDSTn Interrupt Rate Control Registers INTDSTnRATECNTLCountdown ValueLSU n Control Register 0 LSU nREG0 Field Descriptions LSUn Control Register 0 LSUnREG0Addressmsb Bit Ext address fieldsAddresslsb Configoffse T AddresslsbconfigoffsetLSUn Control Register 1 LSUnREG1 LSU n Control Register 1 LSU nREG1 Field DescriptionsLSU n Control Register 2 LSU nREG2 Field Descriptions LSUn Control Register 2 LSUnREG2Dspaddress 32b DSP byte addressLSU n Control Register 3 LSU nREG3 Field Descriptions LSUn Control Register 3 LSUnREG3Bytecount LSUn Control Register 4 LSUnREG4 Field Descriptions LSUn Control Register 4 LSUnREG4LSU n Control Register 5 LSU nREG5 Field Descriptions LSUn Control Register 5 LSUnREG5Drbllinfo Hopcount PackettypeLSUn Control Register 6 LSUnREG6 Field Descriptions LSUn Control Register 6 LSUnREG6Completioncode BSY CompletioncFlowmask LSU Congestion Control Flow Mask n Lsuflowmasks nTxhdp Txcp Rxhdp Queue Receive DMA Completion Pointer Registers QUEUEnRXDMACP Queue Receive DMA Completion Pointer Registers QUEUEnRXDMACPTransmit Queue Teardown Register Txqueueteardown QUEUE3FLOWMASK QUEUE2FLOWMASK QUEUE1FLOWMASK QUEUE0FLOWMASKQUEUE5FLOWMASK QUEUE4FLOWMASK QUEUE7FLOWMASK QUEUE6FLOWMASKMask QUEUE15FLOWMASK QUEUE14FLOWMASKReceive Queue Teardown Register Rxqueueteardown Receive Queue Teardown Register RxqueueteardownReceive Cppi Control Register Rxcppicntl Field Descriptions Receive Cppi Control Register Rxcppicntl3NUMMSGS Txqueuemap3QUEUEPTR 2NUMMSGS7QUEUEPTR 7NUMMSGS6NUMMSGS 6QUEUEPTR11QUEUEPTR 11NUMMSGS10NUMMSGS 10QUEUEPTR15QUEUEPTR 15NUMMSGS14NUMMSGS 14QUEUEPTRMailbox-to-Queue Mapping Register Ln RXUMAPLn Mailbox-to-Queue Mapping Register Hn RXUMAPHn Flowcntlid Flow Control Table Entry Registers FLOWCNTLnDevice Identity CAR Devid Field Descriptions Device Identity CAR DevidDevice Information CAR Devinfo Field Descriptions Device Information CAR DevinfoDevicerev Vendor supply device revisionAssembly Identity CAR Asblyid Field Descriptions Assembly Identity CAR AsblyidAssembly Information CAR Asblyinfo Field Descriptions Assembly Information CAR AsblyinfoProcessing Element Features CAR Pefeat Field Descriptions Processing Element Features CAR PefeatSource Operations CAR Srcop Field Descriptions Source Operations CAR SrcopDestination Operations CAR Destop Field Descriptions Destination Operations CAR DestopExtendedaddress Processing Element Logical Layer Control CSR PellctlIngcontrol RessingcontLcsba Local Configuration Space Base Address 0 CSR LclcfghbarLocal Configuration Space Base Address 1 CSR Lclcfgbar Local Configuration Space Base Address 1 CSR LclcfgbarBase Device ID CSR Baseid Field Descriptions Base Device ID CSR BaseidHostbasedeviceid Host Base Device ID Lock CSR HostbaseidlockHostbasede ViceidComponent Tag CSR Comptag Field Descriptions Component Tag CSR ComptagComponenttag Efid EfptrPort Link Time-Out Control CSR Spltctl Port Link Timeout Control CSR Spltctl Field DescriptionsPort Response Time-Out Control CSR Sprtctl Port Response Time-Out Control CSR SprtctlPort General Control CSR Spgenctl Field Descriptions Port General Control CSR SpgenctlCommand Port Link Maintenance Request CSR n SPnLMREQPort Link Maintenance Response CSR n SPnLMRESP Port Local AckID Status CSR n SPnACKIDSTAT Port Error and Status CSR n SPnERRSTAT Field Descriptions Port Error and Status CSR n SPnERRSTATPortuninitia PortokLized Port Control CSR n SPnCTL Field Descriptions Port Control CSR n SPnCTLNable Port Control CSR n SP nCTL Field DescriptionsError Reporting Block Header Errrptbh Field Descriptions Error Reporting Block Header ErrrptbhLogical/Transport Layer Error Detect CSR Errdet Logical/Transport Layer Error Enable CSR Erren ADDRESS6332 Logical/Transport Layer High Address Capture CSR Haddrcapt50 bit addresses ADDRESS313 Logical/Transport Layer Address Capture CSR AddrcaptXamsbs Msbdestid Destid Logical/Transport Layer Device ID Capture CSR IdcaptMsbsourceid Sourceid MsbdestidFtype Ttype Msginfo Logical/Transport Layer Control Capture CSR CtrlcaptImpspecific FtypePort-Write Target Device ID CSR Pwtgtid Field Descriptions Port-Write Target Device ID CSR PwtgtidDeviceidmsb DeviceidPort Error Detect CSR n SPnERRDET Field Descriptions Port Error Detect CSR n SPnERRDETPort Error Rate Enable CSR n SPnRATEEN Field Descriptions Port Error Rate Enable CSR n SPnRATEENPort n Attributes Error Capture CSR 0 SPnERRATTRCAPTDBG0 CAPTURE0 CAPTURE0CAPTURE1 CAPTURE1CAPTURE2 CAPTURE2CAPTURE3 CAPTURE3Port Error Rate CSR n SPnERRRATE Field Descriptions Port Error Rate CSR n SPnERRRATEPort Error Rate Threshold CSR n SPnERRTHRESH Discoverytimer Port IP Discovery Timer in 4x mode SpipdiscoverytimerPwtimer DiscoverytiPort IP Mode CSR Spipmode Field Descriptions Port IP Mode CSR SpipmodeRsten Port IP Mode CSR Spipmode Field DescriptionsSerial Port IP Prescalar Ipprescal Field Descriptions Serial Port IP Prescalar IpprescalPrescale Pwcapt Port-Write-In Capture CSR n SPIPPWINCAPTnPort Reset Option CSR n SP nRSTOPT Field Descriptions Port Reset Option CSR n SPnRSTOPTPortid Port Control Independent Register n SPnCTLINDEP Maxretryer MaxretryenMaxretryth IrqenPort Silence Timer n SPnSILENCETIMER Field Descriptions Port Silence Timer n SPnSILENCETIMERSilencetimer Multevntcs MultevntcsPort Control Symbol Transmit n SP nCSTX Field Descriptions Port Control Symbol Transmit n SPnCSTXImportant Notice

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