Texas Instruments TMS320C645x manual Reset and Power Down State, Message Passing

Page 40

www.ti.com

SRIO Functional Description

So the general flow is as follows:

∙Previously, the control/command registers were written and the request packet was sent

∙Response Packet Type13, Trans != 0001b arrives at module interface, and is handled sequentially (not based on priority)

∙targetTID is examined to determine routing of a response to the appropriate core

∙The status field of the response packet is checked for ERROR, RETRY or DONE

∙If the field is DONE, it submits DMA bus request and transmits the payload (if any) to DSP address. If the field is ERROR/RETRY, it sets an interrupt

∙Command registers are released (BSY = 0)

∙Optional Interrupt to CPU notifying packet reception

2.3.3.4Reset and Power Down State

Upon reset, the Load/Store module must clear the command register fields and wait for a write by the CPU.

The Load/Store module can be powered down if the direct I/O protocol is not being supported in the application. For example, if the messaging protocol is being used for data transfers, powering down the Load/Store module will save power. In this situation, the command registers should be powered down and inaccessible. Clocks should be gated to these blocks while in the power down state.

2.3.4Message Passing

With message passing, a destination address is not specified. Instead, a mailbox identifier is used within the RapidIO packet. The mailbox is controlled and mapped to memory by the local (destination) device. The message passing within RapidIO specifies 4 mailbox locations. Each mailbox can contain 4 separate transactions (or letters), effectively providing 16 messages. Single packet messages provide 64 mailboxes with 4 letters, effectively providing 256 messages. Mailboxes can be defined for different data types or priorities. The advantage of message passing is that the source device does not require any knowledge of the destination device’s memory map. The DSP contains Buffer Descriptions Tables for each mailbox. These tables define a memory map and pointers for each mailbox. Messages are transferred to the appropriate memory locations via the DMA.

The CPPI (Communications Port Programming Interface) module serves as the incoming and outgoing message passing protocol engine.

The following rules exist for all CPPI traffic:

∙One buffer descriptor per message (each buffer descriptor consists of 4 words or 16 bytes)

∙Requires contiguous memory space for multi-segment Read/Write operations

–Fixed buffer sizes (configured to handle application'smax message size)

∙An ERROR response is sent if the RX message is too big for the allotted buffer sizes

–Subsequent ERROR responses will be sent for all segments of that message

∙An ERROR response is sent if the mailbox is not mapped, or mapped to a non-existent queue

∙An ERROR response is sent if the mailbox is mapped, but the queue is not initialized (RX DMA State HDP not written), or the queue is disabled (Teardown)

∙An ERROR response is sent if the RX buffer descriptor queue has no empty buffers (overflow)

∙Out-of-order responses are allowed

∙RETRY response will be issued to the first received segment of a multi-segment message when the RX queue is busy servicing another request

–Subsequent RETRY responses may have to be sent for received pipeline segments or additional pipelined messages to the same queue

∙Inorder message reception for dedicated flows is mode programmable

∙A queue is needed for each supported simultaneous multi-segment RX message

∙Supports a minimum of 1.25KB SRAM (64 buffer descriptors)

∙Transmit must be able to RETRY any given segment of a transmitted message

∙A Dest_id is equal to port for TX operations, the same Dest_Id is not accessible from multiple ports

40

Serial RapidIO (SRIO)

SPRU976 –March 2006

Page 39 Page 41
Image 40
Page 39 Page 41
Contents Users Guide Submit Documentation Feedback Contents Errrstevnticrr Base Device ID CSR Baseid List of Figures Load/Store Module Interrupt Condition Routing Registers 150 Port Error Rate Threshold CSR n SP n Errthresh List of Tables LSUn Control Register 0 LSUnREG0 Field Descriptions Base Device ID CSR Baseid Field Descriptions Read This First General RapidIO System RapidIO Architectural HierarchyOverview RapidIO Interconnect Architecture 3 1x/4x LP-SerialRapidIO Feature Support in Srio Features Supported in SrioFeatures Not Supported StandardsExternal Devices Requirements RapidIO Documents and LinksOverview Peripheral Data FlowSrio Packets Operation SequenceOperation Sequence Example Packet Streaming WriteControl Symbols 4x RapidIO Packet Data Stream Streaming-Write ClassPacket Type Srio Packet Ftype/TtypeFtype Ttype Packet Type Srio Pins Block DiagramFunctional Operation Pin DescriptionSrio Conceptual Block Diagram Serdes and its Configurations Enabling the PLLBits of Serdescfg nCNTL Register 0x120 0x12c Bit Name Value DescriptionLine Rate versus PLL Output Clock Frequency Bits of Serdescfg nCNTL Register 0x120 0x12cRate Bit Effects Enabling the Receiver Frequency Range versus MPYBits of Serdescfgrx nCNTL Registers Bits of SERDESCFGRXnCNTL Registers Disabled. Loss of signal detection disabledBit Field Value Description 1514 EQ Bits Enabling the TransmitterBits of Serdescfgtx nCNTL Registers CFGRX2219 Low Freq GainSwing Bits Bits of Serdescfgtx nCNTL RegistersDE Bits Serdes Configuration Example DirectIOControl/Command Register Field Mapping RapidIO Packet Header FieldControl/Command Register RapidIO Packet Header Field Status FieldsStatus Field Function BSYLSU Registers Timing Example Burst Nwriter Detailed Data Path DescriptionTX Operation Write TransactionsRead Transactions Segmentation RX OperationReset and Power Down State Message PassingCppi RX Scheme for RapidIO Queue Mapping Table Address Offset 0x0800 0x08FC Queue Mapping Register Rxumapl n Bit Name DescriptionRX Buffer Descriptor Fields RX Buffer Descriptor Field Descriptions Field DescriptionRX Buffer Descriptor Field Descriptions Field DescriptionRX Cppi Mode Explanation Cppi Boundary Diagram TX Buffer Descriptor Fields TX Buffer Descriptor Field DefinitionsUses this bit to reclaim buffers Ssize Name Bit Access Reset Value Description TXQUEUECNTL0- Address Offset 0x7E0TXQUEUECNTL1- Address Offset 0x7E4 TXQUEUECNTL2- Address Offset 0x7E8TXQueueMap10 2316 0x0A Detailed Data Path Description RX Operation Message Passing Software RequirementsTX Operation Queue Mapping Initialization ExampleRX Buffer Descriptor TX Buffer Descriptor NDPMaintenance Start Message PassingDoorbell Doorbell OperationCongestion Control Detailed DescriptionName Bit Transmit Source Flow Control Masks Configuration Bus Example EndiannessReset DMA ExampleEnable and Enable Status Registers Reset SummaryBLK8ENSTA BLK7ENSTA Enable and Enable Status Bit Field Descriptions EnstatGblen BLK0ENBLK1EN BLK1ENSTATBLK2EN BLK2ENSTATSoftware Shutdown Details EmulationBLK8ENSTAT Peren Soft FreeEnabling the Srio Peripherals Emulation Control SignalsPeren Peripheral Initializations 11.2 PLL, Ports, Device ID and Data Rate InitializationsSet Device ID Registers Assert the Peren bit to enable logical layer data flow Read register to check portx1-4 OK bitBootload Capability ConfigurationBootload Data Movement Device WakeupMSG REQ ERRCPU Interrupts General DescriptionInterrupt Condition Control Registers Interrupt Source Configuration Options Where ICS0 Doorbell1, bit 0, through ICS15 Doorbell1, bit Interrupt Conditions LSU Interrupt Condition Clear Registers Iccr Address Offset ICS11 ICS10 ICS9 ICS8 ICS2 ICS1 ICS0ICC11 ICC10 ICC9 ICC8 ICC2 ICC1 ICC0Interrupt Condition Routing Options DOORBELL0ICRR2 Address OffsetLSUICRR2 Address Offset 0x02E8 LSUICRR1 Address Offset 0x02E4LSUICRR3 Address Offset 0x02EC Interrupt Status Decode Registers ERRRSTEVNTICRR2 Address Offset 0x02F4ERRRSTEVNTICRR3 Address Offset 0x02F8 ICR2 ICR1 ICR0Sharing of Isdr Bits Interrupt Pacing Interrupt GenerationISDR3 ISDR2 ISDR1 ISDR9 ISDR8 ISDR7 ISDR6 ISDR5 ISDR4 ISDR0 Interrupt Handling INTDSTnRATECNTL Interrupt Rate Control RegisterInterrupt Conditions Serial Rapid IO Srio Registers IntroductionOffset Acronym Register Description Serial Rapid IO Srio Registers Offset Acronym Register DescriptionLSUICRR3 ErrrstevnticRR2 RR3LSU3REG1 QUEUE1TXDMAC QUEUE2TXDMACQUEUE3TXDMAC QUEUE4TXDMACQUEUE12RXDMA Txcppiflowma SKS6SKS7 RxqueuetearRXUMAPL18 RXUMAPH18RXUMAPL19 RXUMAPH19Asblyid AsblyinfoPefeat SrcopSP0ERRATTRCA PTDBG0SP0ERRCAPTDB SP0ERRRATETimer SP3ERRRATESP3ERRTHRESH SpipdiscoveryPeripheral Identification Register PID Peripheral ID Register PID Field DescriptionsType Class REVPeripheral Control Register PCR Peripheral Control Register PCR Field DescriptionsPere Soft Free Bit FieldPeripheral Settings Control Register Persetcntl Cbatranspr 1XMODEPrescalerse LectENPLL2 ENPLL3ENPLL1 Peripheral Global Enable Register Gblen Peripheral Global Enable Register Gblen Field DescriptionsPeripheral Global Enable Status Register Gblenstat GBLENS TATBlock n Enable Register BLKnEN Block n Enable Register BLKnEN Field DescriptionsBlock n Enable Status Register BLKnENSTAT Block n Enable Status Register BLKnENSTATRapidIO DEVICEID1 Register DEVICEIDREG1 RapidIO DEVICEID1 Register DEVICEIDREG1 Field Descriptions8BNODEID 16BNODEIDRapidIO DEVICEID2 Register DEVICEIDREG2 RapidIO DEVICEID2 Register DEVICEIDREG2 Field DescriptionsPacket Forwarding Register n for 16b DeviceIDs PF16BCNTLn Packet Forwarding Register n for 8b DeviceIDs PF8BCNTLn CDR LOS Align Term Invpa Rate BuswidthCFGRX2219 Low Freq Gain Zero Freq at e28 min Swing Invpa Rate Buswidth EnftEntx Swing Bits DE BitsCFGTX119 Amplitude mV dfpp CFGTX1512 Amplitude ReductionSerdes Macro Configuration Register n SERDESCFGnCNTL MPY EnpllRIOCLK/RIOCLK MPYDOORBELLn Interrupt Status Register DOORBELLnICSR DOORBELLn Interrupt Status Register DOORBELLnICSRDOORBELLn Interrupt Clear Register DOORBELLnICCR DOORBELLn Interrupt Clear Register DOORBELLnICCRRX Cppi Interrupt Status Register Rxcppiicsr RX Cppi Interrupt Status Register RxcppiicsrRX Cppi Interrupt Clear Register Rxcppiiccr RX Cppi Interrupt Clear Register RxcppiiccrTX Cppi Interrupt Status Register Txcppiicsr TX Cppi Interrupt Status Register TxcppiicsrTX Cppi Interrupt Clear Register Txcppiiccr TX Cppi Interrupt Clear Register TxcppiiccrLSU Status Interrupt Register Lsuicsr Field Descriptions LSU Status Interrupt Register LsuicsrICS31-0 Load/Store module interrupt condition status bits LSU Clear Interrupt Register LSU Iccr Field Descriptions LSU Clear Interrupt Register LSU IccrICS31-0 Load/Store module interrupt clear bits 31-17 126 DOORBELLn Interrupt Condition Routing Register DOORBELLnICRR 128 RX Cppi Interrupt Condition Routing Register Rxcppi Icrr ICR RX Cppi Interrupt condition routing bitsRX Cppi Interrupt Condition Routing Register Rxcppi ICRR2 RX Cppi Interrupt Condition Routing Register Rxcppi ICRR2TX Cppi Interrupt Condition Routing Register Txcppi Icrr ICR TX Cppi Interrupt condition routing bitsTX Cppi Interrupt Condition Routing Register Txcppi ICRR2 TX Cppi Interrupt Condition Routing Register Txcppi ICRR2LSU Module Interrupt Condition Routing Register 0 LSUICRR0 ICRLSU Module Interrupt Condition Routing Register 1 LSUICRR1 LSU Module Interrupt Condition Routing Register 1 LSUICRR1LSU Module Interrupt Condition Routing Register 2 LSUICRR2 LSU Module Interrupt Condition Routing Register 2 LSUICRR2LSU Module Interrupt Condition Routing Register 3 LSUICRR3 LSU Module Interrupt Condition Routing Register 3 LSUICRR3Errrstevnticrr Errrstevnticrr Field DescriptionsERRRSTEVNTICRR2 Field Descriptions ICR11ERRRSTEVNTICRR3 ERRRSTEVNTICRR3 Field DescriptionsINTDSTn Interrupt Status Decode Registers INTDSTnDECODE INTDSTn Interrupt Status Decode Registers INTDSTnDECODEINTDSTn Interrupt Rate Control Registers INTDSTnRATECNTL CountdownvalueCountdown ValueLSUn Control Register 0 LSUnREG0 LSU n Control Register 0 LSU nREG0 Field DescriptionsAddressmsb Bit Ext address fieldsAddresslsbconfigoffset Addresslsb Configoffse TLSUn Control Register 1 LSUnREG1 LSU n Control Register 1 LSU nREG1 Field DescriptionsLSUn Control Register 2 LSUnREG2 LSU n Control Register 2 LSU nREG2 Field DescriptionsDspaddress 32b DSP byte addressLSU n Control Register 3 LSU nREG3 Field Descriptions LSUn Control Register 3 LSUnREG3Bytecount LSUn Control Register 4 LSUnREG4 LSUn Control Register 4 LSUnREG4 Field DescriptionsLSUn Control Register 5 LSUnREG5 LSU n Control Register 5 LSU nREG5 Field DescriptionsDrbllinfo Hopcount PackettypeLSUn Control Register 6 LSUnREG6 LSUn Control Register 6 LSUnREG6 Field DescriptionsCompletioncode BSY CompletioncLSU Congestion Control Flow Mask n Lsuflowmasks n FlowmaskTxhdp Txcp Rxhdp Queue Receive DMA Completion Pointer Registers QUEUEnRXDMACP Queue Receive DMA Completion Pointer Registers QUEUEnRXDMACPTransmit Queue Teardown Register Txqueueteardown QUEUE1FLOWMASK QUEUE0FLOWMASK QUEUE3FLOWMASK QUEUE2FLOWMASKQUEUE5FLOWMASK QUEUE4FLOWMASK QUEUE7FLOWMASK QUEUE6FLOWMASKQUEUE15FLOWMASK QUEUE14FLOWMASK MaskReceive Queue Teardown Register Rxqueueteardown Receive Queue Teardown Register RxqueueteardownReceive Cppi Control Register Rxcppicntl Receive Cppi Control Register Rxcppicntl Field DescriptionsTxqueuemap 3NUMMSGS3QUEUEPTR 2NUMMSGS7NUMMSGS 7QUEUEPTR6NUMMSGS 6QUEUEPTR11NUMMSGS 11QUEUEPTR10NUMMSGS 10QUEUEPTR15NUMMSGS 15QUEUEPTR14NUMMSGS 14QUEUEPTRMailbox-to-Queue Mapping Register Ln RXUMAPLn Mailbox-to-Queue Mapping Register Hn RXUMAPHn Flow Control Table Entry Registers FLOWCNTLn FlowcntlidDevice Identity CAR Devid Device Identity CAR Devid Field DescriptionsDevice Information CAR Devinfo Device Information CAR Devinfo Field DescriptionsDevicerev Vendor supply device revisionAssembly Identity CAR Asblyid Assembly Identity CAR Asblyid Field DescriptionsAssembly Information CAR Asblyinfo Assembly Information CAR Asblyinfo Field DescriptionsProcessing Element Features CAR Pefeat Processing Element Features CAR Pefeat Field DescriptionsSource Operations CAR Srcop Source Operations CAR Srcop Field DescriptionsDestination Operations CAR Destop Destination Operations CAR Destop Field DescriptionsProcessing Element Logical Layer Control CSR Pellctl ExtendedaddressIngcontrol RessingcontLocal Configuration Space Base Address 0 CSR Lclcfghbar LcsbaLocal Configuration Space Base Address 1 CSR Lclcfgbar Local Configuration Space Base Address 1 CSR LclcfgbarBase Device ID CSR Baseid Base Device ID CSR Baseid Field DescriptionsHost Base Device ID Lock CSR Hostbaseidlock HostbasedeviceidHostbasede ViceidComponent Tag CSR Comptag Field Descriptions Component Tag CSR ComptagComponenttag Efptr EfidPort Link Timeout Control CSR Spltctl Field Descriptions Port Link Time-Out Control CSR SpltctlPort Response Time-Out Control CSR Sprtctl Port Response Time-Out Control CSR SprtctlPort General Control CSR Spgenctl Port General Control CSR Spgenctl Field DescriptionsPort Link Maintenance Request CSR n SPnLMREQ CommandPort Link Maintenance Response CSR n SPnLMRESP Port Local AckID Status CSR n SPnACKIDSTAT Port Error and Status CSR n SPnERRSTAT Port Error and Status CSR n SPnERRSTAT Field DescriptionsPortuninitia PortokLized Port Control CSR n SPnCTL Port Control CSR n SPnCTL Field DescriptionsPort Control CSR n SP nCTL Field Descriptions NableError Reporting Block Header Errrptbh Error Reporting Block Header Errrptbh Field DescriptionsLogical/Transport Layer Error Detect CSR Errdet Logical/Transport Layer Error Enable CSR Erren ADDRESS6332 Logical/Transport Layer High Address Capture CSR Haddrcapt50 bit addresses ADDRESS313 Logical/Transport Layer Address Capture CSR AddrcaptXamsbs Logical/Transport Layer Device ID Capture CSR Idcapt Msbdestid DestidMsbsourceid Sourceid MsbdestidLogical/Transport Layer Control Capture CSR Ctrlcapt Ftype Ttype MsginfoImpspecific FtypePort-Write Target Device ID CSR Pwtgtid Port-Write Target Device ID CSR Pwtgtid Field DescriptionsDeviceidmsb DeviceidPort Error Detect CSR n SPnERRDET Port Error Detect CSR n SPnERRDET Field DescriptionsPort Error Rate Enable CSR n SPnRATEEN Port Error Rate Enable CSR n SPnRATEEN Field DescriptionsPort n Attributes Error Capture CSR 0 SPnERRATTRCAPTDBG0 CAPTURE0 CAPTURE0CAPTURE1 CAPTURE1CAPTURE2 CAPTURE2CAPTURE3 CAPTURE3Port Error Rate CSR n SPnERRRATE Port Error Rate CSR n SPnERRRATE Field DescriptionsPort Error Rate Threshold CSR n SPnERRTHRESH Port IP Discovery Timer in 4x mode Spipdiscoverytimer DiscoverytimerPwtimer DiscoverytiPort IP Mode CSR Spipmode Port IP Mode CSR Spipmode Field DescriptionsPort IP Mode CSR Spipmode Field Descriptions RstenSerial Port IP Prescalar Ipprescal Field Descriptions Serial Port IP Prescalar IpprescalPrescale Port-Write-In Capture CSR n SPIPPWINCAPTn PwcaptPort Reset Option CSR n SP nRSTOPT Field Descriptions Port Reset Option CSR n SPnRSTOPTPortid Port Control Independent Register n SPnCTLINDEP Maxretryen MaxretryerMaxretryth IrqenPort Silence Timer n SPnSILENCETIMER Field Descriptions Port Silence Timer n SPnSILENCETIMERSilencetimer Multevntcs MultevntcsPort Control Symbol Transmit n SPnCSTX Port Control Symbol Transmit n SP nCSTX Field DescriptionsImportant Notice
Related manuals
Manual 27 pages 54.69 Kb
Top Page Image Contents