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Interrupt Conditions
Figure 54. Sharing of ISDR Bits
ISDR | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
LSU
Error,
Tx
Rx
ISDR | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Doorbell
Doorbell
Doorbell
Doorbell
As an example, if bit 29 of the ISDR is set, this indicates that there is a pending interrupt on either the TX CPPI queue 2 or RX CPPI queue 2. Figure 55 illustrates the decode routing.
TX
2
RX
2
Figure 55. Example Diagram of Interrupt Status Decode Register Mapping
TX |
|
| Interrupt |
0 | Decode |
1 | 29 |
2 |
|
3 | 29 |
| |
4 |
|
5 | 29 |
| |
6 |
|
7 | 29 |
| |
TX |
|
| 29 |
0 |
|
1 |
|
| 29 |
2 |
|
3 |
|
| 29 |
4 |
|
5 |
|
| 29 |
6 |
|
7 |
|
INTDST0
INTDST1
INTDST2
INTDST3
INTDST4
INTDST5
INTDST6
INTDST7
84 | Serial RapidIO (SRIO) | SPRU976 |