Texas Instruments TMS320C645x manual Segmentation, RX Operation

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SRIO Functional Description

Segmentation:

The LSU handles two types of segmentation of outbound requests. The first type is when the Byte_Count of Read/Write requests exceeds 256 bytes (up to 4KB). The second type is when Read/Write request RapidIO address is non-64b aligned. In both cases, the outgoing request must be broken up into multiple RapidIO request packets. For example, assume that the CPU wants to perform a 1KB store operation to an external RapidIO device. After setting up the LSU registers, the CPU performs one write to the LSU_Reg5 register. The peripheral hardware then segments the store operation into four RapidIO write packets of 256B each, and calculates the 64b-aligned RapidIO address, WRSIZE, and WDPTR as required for each packet. This example requires four outbound handles to be assigned and four DMA transmit requests. The LSU registers cannot be released until all posted request packets are passed to the TX FIFOs. Alternatively, for non-posted operations, such as CPU loads, all packet responses must be received before the LSU registers are released.

2.3.3.3RX Operation

Response packets are always type 13 RapidIO packets. All response packets with transaction types not equal to 0001b are routed to the LSU block sequentially in order of reception. These packets may have a payload, depending on the type of corresponding request packet that was originally sent. Due to the nature of RapidIO switch fabric systems, response packets can arrive in any order. The data payload, if any, and header data is moved from the RX FIFO to the shared RX buffer. The DestID field of the packet is examined to determine which core and corresponding set of registers are waiting for the response. Remember, there can be only one outstanding request per core. Any payload data is moved from the shared RX buffer pool into memory through normal DMA bus operations.

Registers for all non-posted operations should only be held for a finite amount of time to avoid blocking resources when a request or response packet is somehow lost in the switch fabric. This time correlates to the 24-bit Port Response Time-out Control CSR value discussed in sections 5.10.1 and 6.1.2.4 of the serial specification. If the time expires, control/command register resources should be released, and an error is logged in the ERROR MANAGEMENT RapidIO registers. The RapidIO specification states that the maximum time interval (all 1s) is between 3 and 6 seconds. A logical layer timeout occurs if the response packet is not received before a countdown timer (initialized to this CSR value) reaches zero.

Each outstanding packet response timer requires a 4-bit register. The register is loaded with the current timecode when the transaction is sent. Each time the timecode changes, a 4-bit compare is done to the register. If the register becomes equal to the timecode again, without a response being seen, then the transaction has timed out. Essentially, instead of the 24-bit value representing the period of the response timer, the period is now defined as P = (2^24 x 16)/F. This means the countdown timer frequency needs to be 44.7 – 89.5Mhz for a 6 – 3 second response timeout. Because the needed timer frequency is derived from the DMA bus clock (which is device dependent), the hardware supports a programmable configuration register field to properly scale the clock frequency. This configuration register field is described in the Peripheral Setting Control register (Address offset 0x0020).

If a response packet indicates ERROR status, the Load/Store module notifies the CPU by generating an error interrupt for the pending non-posted transaction. If the response has completed successfully, and the Interrupt Req bit is set in the control register, the module generates a CPU servicing interrupt to notify the CPU that the response is available. The control/command registers can be released as soon as the response packet is received by the logical layer. The hardware is not responsible for attempting a retransmission of the non-posted transaction.

If a Doorbell response packet indicates Retry status, the Load/Store module notifies the CPU by generating an interrupt. The control/command registers can be released as soon as the response packet is received by the logical layer. The hardware is not responsible for attempting retransmission of the Doorbell transaction.

SPRU976 –March 2006

Serial RapidIO (SRIO)

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Contents Users Guide Submit Documentation Feedback Contents Errrstevnticrr Base Device ID CSR Baseid List of Figures Load/Store Module Interrupt Condition Routing Registers 150 Port Error Rate Threshold CSR n SP n Errthresh List of Tables LSUn Control Register 0 LSUnREG0 Field Descriptions Base Device ID CSR Baseid Field Descriptions Read This First RapidIO Architectural Hierarchy General RapidIO SystemOverview 3 1x/4x LP-Serial RapidIO Interconnect ArchitectureFeatures Supported in Srio RapidIO Feature Support in SrioRapidIO Documents and Links Features Not SupportedStandards External Devices RequirementsPeripheral Data Flow OverviewOperation Sequence Srio PacketsExample Packet Streaming Write Operation Sequence4x RapidIO Packet Data Stream Streaming-Write Class Control SymbolsSrio Packet Ftype/Ttype Packet TypeFtype Ttype Packet Type Pin Description Srio PinsBlock Diagram Functional OperationSrio Conceptual Block Diagram Bit Name Value Description Serdes and its ConfigurationsEnabling the PLL Bits of Serdescfg nCNTL Register 0x120 0x12cBits of Serdescfg nCNTL Register 0x120 0x12c Line Rate versus PLL Output Clock FrequencyRate Bit Effects Frequency Range versus MPY Enabling the ReceiverBits of Serdescfgrx nCNTL Registers Disabled. Loss of signal detection disabled Bits of SERDESCFGRXnCNTL RegistersBit Field Value Description 1514 CFGRX2219 Low Freq Gain EQ BitsEnabling the Transmitter Bits of Serdescfgtx nCNTL RegistersBits of Serdescfgtx nCNTL Registers Swing BitsDE Bits DirectIO Serdes Configuration ExampleRapidIO Packet Header Field Control/Command Register Field MappingBSY Control/Command Register RapidIO Packet Header FieldStatus Fields Status Field FunctionLSU Registers Timing Detailed Data Path Description Example Burst NwriterWrite Transactions TX OperationRead Transactions RX Operation SegmentationMessage Passing Reset and Power Down StateCppi RX Scheme for RapidIO Queue Mapping Table Address Offset 0x0800 0x08FC Bit Name Description Queue Mapping Register Rxumapl nRX Buffer Descriptor Fields Field Description RX Buffer Descriptor Field DescriptionsField Description RX Buffer Descriptor Field DescriptionsRX Cppi Mode Explanation Cppi Boundary Diagram TX Buffer Descriptor Field Definitions TX Buffer Descriptor FieldsUses this bit to reclaim buffers Ssize TXQUEUECNTL2- Address Offset 0x7E8 Name Bit Access Reset Value DescriptionTXQUEUECNTL0- Address Offset 0x7E0 TXQUEUECNTL1- Address Offset 0x7E4TXQueueMap10 2316 0x0A Detailed Data Path Description Message Passing Software Requirements RX OperationTX Operation Initialization Example Queue MappingRX Buffer Descriptor NDP TX Buffer DescriptorStart Message Passing MaintenanceDoorbell Operation DoorbellDetailed Description Congestion ControlName Bit Transmit Source Flow Control Masks Endianness Configuration Bus ExampleDMA Example ResetReset Summary Enable and Enable Status RegistersBLK8ENSTA BLK7ENSTA BLK0EN Enable and Enable Status Bit Field DescriptionsEnstat GblenBLK2ENSTAT BLK1ENBLK1ENSTAT BLK2ENPeren Soft Free Software Shutdown DetailsEmulation BLK8ENSTATEmulation Control Signals Enabling the Srio PeripheralsPeren 11.2 PLL, Ports, Device ID and Data Rate Initializations Peripheral InitializationsSet Device ID Registers Read register to check portx1-4 OK bit Assert the Peren bit to enable logical layer data flowDevice Wakeup Bootload CapabilityConfiguration Bootload Data MovementERR MSG REQGeneral Description CPU InterruptsInterrupt Condition Control Registers Interrupt Source Configuration Options Where ICS0 Doorbell1, bit 0, through ICS15 Doorbell1, bit Interrupt Conditions LSU Interrupt Condition Clear Registers Iccr Address Offset ICC2 ICC1 ICC0 ICS11 ICS10 ICS9 ICS8ICS2 ICS1 ICS0 ICC11 ICC10 ICC9 ICC8DOORBELL0ICRR2 Address Offset Interrupt Condition Routing OptionsLSUICRR1 Address Offset 0x02E4 LSUICRR2 Address Offset 0x02E8LSUICRR3 Address Offset 0x02EC ICR2 ICR1 ICR0 Interrupt Status Decode RegistersERRRSTEVNTICRR2 Address Offset 0x02F4 ERRRSTEVNTICRR3 Address Offset 0x02F8Sharing of Isdr Bits Interrupt Generation Interrupt PacingISDR3 ISDR2 ISDR1 ISDR9 ISDR8 ISDR7 ISDR6 ISDR5 ISDR4 ISDR0 INTDSTnRATECNTL Interrupt Rate Control Register Interrupt HandlingInterrupt Conditions Introduction Serial Rapid IO Srio RegistersOffset Acronym Register Description Offset Acronym Register Description Serial Rapid IO Srio RegistersRR3 LSUICRR3Errrstevntic RR2LSU3REG1 QUEUE4TXDMAC QUEUE1TXDMACQUEUE2TXDMAC QUEUE3TXDMACQUEUE12RXDMA Rxqueuetear TxcppiflowmaSKS6 SKS7RXUMAPH19 RXUMAPL18RXUMAPH18 RXUMAPL19Srcop AsblyidAsblyinfo PefeatSP0ERRRATE SP0ERRATTRCAPTDBG0 SP0ERRCAPTDBSpipdiscovery TimerSP3ERRRATE SP3ERRTHRESHClass REV Peripheral Identification Register PIDPeripheral ID Register PID Field Descriptions TypeBit Field Peripheral Control Register PCRPeripheral Control Register PCR Field Descriptions Pere Soft FreePeripheral Settings Control Register Persetcntl Lect Cbatranspr1XMODE PrescalerseENPLL3 ENPLL2ENPLL1 Peripheral Global Enable Register Gblen Field Descriptions Peripheral Global Enable Register GblenTAT Peripheral Global Enable Status Register GblenstatGBL ENSBlock n Enable Register BLKnEN Field Descriptions Block n Enable Register BLKnENBlock n Enable Status Register BLKnENSTAT Block n Enable Status Register BLKnENSTAT16BNODEID RapidIO DEVICEID1 Register DEVICEIDREG1RapidIO DEVICEID1 Register DEVICEIDREG1 Field Descriptions 8BNODEIDRapidIO DEVICEID2 Register DEVICEIDREG2 Field Descriptions RapidIO DEVICEID2 Register DEVICEIDREG2Packet Forwarding Register n for 16b DeviceIDs PF16BCNTLn Packet Forwarding Register n for 8b DeviceIDs PF8BCNTLn Term Invpa Rate Buswidth CDR LOS AlignCFGRX2219 Low Freq Gain Zero Freq at e28 min Enft Swing Invpa Rate BuswidthEntx CFGTX1512 Amplitude Reduction Swing BitsDE Bits CFGTX119 Amplitude mV dfppMPY Serdes Macro Configuration Register n SERDESCFGnCNTLMPY Enpll RIOCLK/RIOCLKDOORBELLn Interrupt Status Register DOORBELLnICSR DOORBELLn Interrupt Status Register DOORBELLnICSRDOORBELLn Interrupt Clear Register DOORBELLnICCR DOORBELLn Interrupt Clear Register DOORBELLnICCRRX Cppi Interrupt Status Register Rxcppiicsr RX Cppi Interrupt Status Register RxcppiicsrRX Cppi Interrupt Clear Register Rxcppiiccr RX Cppi Interrupt Clear Register RxcppiiccrTX Cppi Interrupt Status Register Txcppiicsr TX Cppi Interrupt Status Register TxcppiicsrTX Cppi Interrupt Clear Register Txcppiiccr TX Cppi Interrupt Clear Register TxcppiiccrLSU Status Interrupt Register Lsuicsr LSU Status Interrupt Register Lsuicsr Field DescriptionsICS31-0 Load/Store module interrupt condition status bits LSU Clear Interrupt Register LSU Iccr LSU Clear Interrupt Register LSU Iccr Field DescriptionsICS31-0 Load/Store module interrupt clear bits 31-17 126 DOORBELLn Interrupt Condition Routing Register DOORBELLnICRR 128 ICR RX Cppi Interrupt condition routing bits RX Cppi Interrupt Condition Routing Register Rxcppi IcrrRX Cppi Interrupt Condition Routing Register Rxcppi ICRR2 RX Cppi Interrupt Condition Routing Register Rxcppi ICRR2ICR TX Cppi Interrupt condition routing bits TX Cppi Interrupt Condition Routing Register Txcppi IcrrTX Cppi Interrupt Condition Routing Register Txcppi ICRR2 TX Cppi Interrupt Condition Routing Register Txcppi ICRR2ICR LSU Module Interrupt Condition Routing Register 0 LSUICRR0LSU Module Interrupt Condition Routing Register 1 LSUICRR1 LSU Module Interrupt Condition Routing Register 1 LSUICRR1LSU Module Interrupt Condition Routing Register 2 LSUICRR2 LSU Module Interrupt Condition Routing Register 2 LSUICRR2LSU Module Interrupt Condition Routing Register 3 LSUICRR3 LSU Module Interrupt Condition Routing Register 3 LSUICRR3Errrstevnticrr Field Descriptions ErrrstevnticrrICR11 ERRRSTEVNTICRR2 Field DescriptionsERRRSTEVNTICRR3 Field Descriptions ERRRSTEVNTICRR3INTDSTn Interrupt Status Decode Registers INTDSTnDECODE INTDSTn Interrupt Status Decode Registers INTDSTnDECODEValue INTDSTn Interrupt Rate Control Registers INTDSTnRATECNTLCountdownvalue CountdownBit Ext address fields LSUn Control Register 0 LSUnREG0LSU n Control Register 0 LSU nREG0 Field Descriptions AddressmsbLSU n Control Register 1 LSU nREG1 Field Descriptions AddresslsbconfigoffsetAddresslsb Configoffse T LSUn Control Register 1 LSUnREG132b DSP byte address LSUn Control Register 2 LSUnREG2LSU n Control Register 2 LSU nREG2 Field Descriptions DspaddressLSUn Control Register 3 LSUnREG3 LSU n Control Register 3 LSU nREG3 Field DescriptionsBytecount LSUn Control Register 4 LSUnREG4 Field Descriptions LSUn Control Register 4 LSUnREG4Hopcount Packettype LSUn Control Register 5 LSUnREG5LSU n Control Register 5 LSU nREG5 Field Descriptions DrbllinfoCompletionc LSUn Control Register 6 LSUnREG6LSUn Control Register 6 LSUnREG6 Field Descriptions Completioncode BSYFlowmask LSU Congestion Control Flow Mask n Lsuflowmasks nTxhdp Txcp Rxhdp Queue Receive DMA Completion Pointer Registers QUEUEnRXDMACP Queue Receive DMA Completion Pointer Registers QUEUEnRXDMACPTransmit Queue Teardown Register Txqueueteardown QUEUE7FLOWMASK QUEUE6FLOWMASK QUEUE1FLOWMASK QUEUE0FLOWMASKQUEUE3FLOWMASK QUEUE2FLOWMASK QUEUE5FLOWMASK QUEUE4FLOWMASKMask QUEUE15FLOWMASK QUEUE14FLOWMASKReceive Queue Teardown Register Rxqueueteardown Receive Queue Teardown Register RxqueueteardownReceive Cppi Control Register Rxcppicntl Field Descriptions Receive Cppi Control Register Rxcppicntl2NUMMSGS Txqueuemap3NUMMSGS 3QUEUEPTR6QUEUEPTR 7NUMMSGS7QUEUEPTR 6NUMMSGS10QUEUEPTR 11NUMMSGS11QUEUEPTR 10NUMMSGS14QUEUEPTR 15NUMMSGS15QUEUEPTR 14NUMMSGSMailbox-to-Queue Mapping Register Ln RXUMAPLn Mailbox-to-Queue Mapping Register Hn RXUMAPHn Flowcntlid Flow Control Table Entry Registers FLOWCNTLnDevice Identity CAR Devid Field Descriptions Device Identity CAR DevidVendor supply device revision Device Information CAR DevinfoDevice Information CAR Devinfo Field Descriptions DevicerevAssembly Identity CAR Asblyid Field Descriptions Assembly Identity CAR AsblyidAssembly Information CAR Asblyinfo Field Descriptions Assembly Information CAR AsblyinfoProcessing Element Features CAR Pefeat Field Descriptions Processing Element Features CAR PefeatSource Operations CAR Srcop Field Descriptions Source Operations CAR SrcopDestination Operations CAR Destop Field Descriptions Destination Operations CAR DestopRessingcont Processing Element Logical Layer Control CSR PellctlExtendedaddress IngcontrolLcsba Local Configuration Space Base Address 0 CSR LclcfghbarLocal Configuration Space Base Address 1 CSR Lclcfgbar Local Configuration Space Base Address 1 CSR LclcfgbarBase Device ID CSR Baseid Field Descriptions Base Device ID CSR BaseidViceid Host Base Device ID Lock CSR HostbaseidlockHostbasedeviceid HostbasedeComponent Tag CSR Comptag Component Tag CSR Comptag Field DescriptionsComponenttag Efid EfptrPort Link Time-Out Control CSR Spltctl Port Link Timeout Control CSR Spltctl Field DescriptionsPort Response Time-Out Control CSR Sprtctl Port Response Time-Out Control CSR SprtctlPort General Control CSR Spgenctl Field Descriptions Port General Control CSR SpgenctlCommand Port Link Maintenance Request CSR n SPnLMREQPort Link Maintenance Response CSR n SPnLMRESP Port Local AckID Status CSR n SPnACKIDSTAT Port Error and Status CSR n SPnERRSTAT Field Descriptions Port Error and Status CSR n SPnERRSTATPortok PortuninitiaLized Port Control CSR n SPnCTL Field Descriptions Port Control CSR n SPnCTLNable Port Control CSR n SP nCTL Field DescriptionsError Reporting Block Header Errrptbh Field Descriptions Error Reporting Block Header ErrrptbhLogical/Transport Layer Error Detect CSR Errdet Logical/Transport Layer Error Enable CSR Erren Logical/Transport Layer High Address Capture CSR Haddrcapt ADDRESS633250 bit addresses Logical/Transport Layer Address Capture CSR Addrcapt ADDRESS313Xamsbs Msbdestid Logical/Transport Layer Device ID Capture CSR IdcaptMsbdestid Destid Msbsourceid SourceidFtype Logical/Transport Layer Control Capture CSR CtrlcaptFtype Ttype Msginfo ImpspecificDeviceid Port-Write Target Device ID CSR PwtgtidPort-Write Target Device ID CSR Pwtgtid Field Descriptions DeviceidmsbPort Error Detect CSR n SPnERRDET Field Descriptions Port Error Detect CSR n SPnERRDETPort Error Rate Enable CSR n SPnRATEEN Field Descriptions Port Error Rate Enable CSR n SPnRATEENPort n Attributes Error Capture CSR 0 SPnERRATTRCAPTDBG0 CAPTURE0 CAPTURE0CAPTURE1 CAPTURE1CAPTURE2 CAPTURE2CAPTURE3 CAPTURE3Port Error Rate CSR n SPnERRRATE Field Descriptions Port Error Rate CSR n SPnERRRATEPort Error Rate Threshold CSR n SPnERRTHRESH Discoveryti Port IP Discovery Timer in 4x mode SpipdiscoverytimerDiscoverytimer PwtimerPort IP Mode CSR Spipmode Field Descriptions Port IP Mode CSR SpipmodeRsten Port IP Mode CSR Spipmode Field DescriptionsSerial Port IP Prescalar Ipprescal Serial Port IP Prescalar Ipprescal Field DescriptionsPrescale Pwcapt Port-Write-In Capture CSR n SPIPPWINCAPTnPort Reset Option CSR n SPnRSTOPT Port Reset Option CSR n SP nRSTOPT Field DescriptionsPortid Port Control Independent Register n SPnCTLINDEP Irqen MaxretryenMaxretryer MaxretrythPort Silence Timer n SPnSILENCETIMER Port Silence Timer n SPnSILENCETIMER Field DescriptionsSilencetimer Multevntcs MultevntcsPort Control Symbol Transmit n SP nCSTX Field Descriptions Port Control Symbol Transmit n SPnCSTXImportant Notice
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