Texas Instruments TMS320C645x manual Example Burst Nwriter, Detailed Data Path Description

Page 36

SRIO Functional Description

Figure 12. Example Burst NWRITE_R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LSUn_REG2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DSP Address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LSUn_REG4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OutPortID

 

Priority

 

xambs

 

 

ID

 

 

DestID

 

 

 

RSV

 

Interrupt

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31

30

29

28

27

26

25

24

23

8

7

1

 

0

 

 

 

 

 

 

 

 

LSUn_REG5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Drbll

Hop

 

 

 

Packet

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31

16

15

8

7

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Count

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LSUn_REG0

 

 

 

 

 

 

 

 

 

 

 

translator

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LSUn_REG1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RapioIO Address/Config_offset

 

 

 

 

 

 

 

 

rdsize/

 

 

rdptr/

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

wsize

 

 

wptr

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NodeID

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Count*8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ackID

rsv

prio

tt

 

ftype

 

destID

sourceID

trans

 

wrsize

srcTID

 

ext

 

 

address

 

wr

xamsbs

payload

 

CRC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

3

 

2

2

4

8

 

8

4

 

4

 

8

32

29

 

1

2

 

 

 

 

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LSUn_REG3

Byte

TXfer

www.ti.com

DMA Read

Source Address

Destination Address

Count

For WRITE commands, the payload is combined with the header information from the control/command registers and buffered in the shared TX buffer resource pool. Finally, it is forwarded to the TX FIFO for transmission. READ commands have no payload. In this case, only the control/command register fields are buffered and used to create a RapidIO NREAD packet, which is forwarded to the TX FIFO. Corresponding response packet payloads from READ transactions are buffered in the shared RX buffer resource pool when forwarded from the receive ports. Both posted and non-posted operations rely on the OutPortID command register field to specify the appropriate output port/FIFO.

The data is burst internally to the Load/Store module at the DMA clock rate.

2.3.3.1Detailed Data Path Description

The Load/Store module is for generating all outgoing RapidIO Direct I/O packets. Any read or write transaction, other than the messaging protocol, uses this interface. In addition, outgoing DOORBELL packets are generated through this interface.

The data path for this module uses DMA bus as the DMA interface. The configuration bus is used by the CPU to access the control/command registers. The registers contain transfer descriptors that are needed to initiate READ and WRITE packet generation. After the transfer descriptors are written, flow control status is queried. The unit examines the DESTID and PRIORITY fields of LSUn_REG4 to determine if that flow has been Xoffd. Additionally, the free buffer status of the TX FIFO is checked (based on the OutPortID register field). Only after the flow control access is granted, and a TX FIFO buffer has been allocated, can a DMA bus read command be issued for payload data to be moved into the shared TX buffer pool. Data is moved from the shared buffer pool to the appropriate output TX FIFO in simple sequential order based on completion of the DMA bus transaction. However, if fabric congestion occurs, priority can affect the order in which the data leaves the TX FIFOs.

Here a reordering mechanism exists, which transmits the highest priority packets first if RETRY acknowledges. Once in the FIFO, the data is guaranteed to be transmitted through the pins. Alternatively, if an intended flow has been shut down, the peripheral signals the CPU with an interrupt to notify that the packet was not sent and sets the completion code to 010b in the status register. The registers must be held until the interrupt service routine is complete before the BSY signal is released (BSY=0 in LSUn_REG6) and the CPU can then rewrite or overwrite the transfer descriptors with new data. Figure 13 illustrates the data path and buffering that is required to support the Load/Store Module.

36

Serial RapidIO (SRIO)

SPRU976 –March 2006

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Contents Users Guide Submit Documentation Feedback Contents Errrstevnticrr Base Device ID CSR Baseid List of Figures Load/Store Module Interrupt Condition Routing Registers 150 Port Error Rate Threshold CSR n SP n Errthresh List of Tables LSUn Control Register 0 LSUnREG0 Field Descriptions Base Device ID CSR Baseid Field Descriptions Read This First General RapidIO System RapidIO Architectural HierarchyOverview RapidIO Interconnect Architecture 3 1x/4x LP-SerialRapidIO Feature Support in Srio Features Supported in SrioFeatures Not Supported StandardsExternal Devices Requirements RapidIO Documents and LinksOverview Peripheral Data FlowSrio Packets Operation SequenceOperation Sequence Example Packet Streaming WriteControl Symbols 4x RapidIO Packet Data Stream Streaming-Write ClassSrio Packet Ftype/Ttype Packet TypeFtype Ttype Packet Type Srio Pins Block DiagramFunctional Operation Pin DescriptionSrio Conceptual Block Diagram Serdes and its Configurations Enabling the PLLBits of Serdescfg nCNTL Register 0x120 0x12c Bit Name Value DescriptionBits of Serdescfg nCNTL Register 0x120 0x12c Line Rate versus PLL Output Clock FrequencyRate Bit Effects Frequency Range versus MPY Enabling the ReceiverBits of Serdescfgrx nCNTL Registers Disabled. Loss of signal detection disabled Bits of SERDESCFGRXnCNTL RegistersBit Field Value Description 1514 EQ Bits Enabling the TransmitterBits of Serdescfgtx nCNTL Registers CFGRX2219 Low Freq GainBits of Serdescfgtx nCNTL Registers Swing BitsDE Bits Serdes Configuration Example DirectIOControl/Command Register Field Mapping RapidIO Packet Header FieldControl/Command Register RapidIO Packet Header Field Status FieldsStatus Field Function BSYLSU Registers Timing Example Burst Nwriter Detailed Data Path DescriptionTX Operation Write TransactionsRead Transactions Segmentation RX OperationReset and Power Down State Message PassingCppi RX Scheme for RapidIO Queue Mapping Table Address Offset 0x0800 0x08FC Queue Mapping Register Rxumapl n Bit Name DescriptionRX Buffer Descriptor Fields RX Buffer Descriptor Field Descriptions Field DescriptionRX Buffer Descriptor Field Descriptions Field DescriptionRX Cppi Mode Explanation Cppi Boundary Diagram TX Buffer Descriptor Fields TX Buffer Descriptor Field DefinitionsUses this bit to reclaim buffers Ssize Name Bit Access Reset Value Description TXQUEUECNTL0- Address Offset 0x7E0TXQUEUECNTL1- Address Offset 0x7E4 TXQUEUECNTL2- Address Offset 0x7E8TXQueueMap10 2316 0x0A Detailed Data Path Description Message Passing Software Requirements RX OperationTX Operation Initialization Example Queue MappingRX Buffer Descriptor TX Buffer Descriptor NDPMaintenance Start Message PassingDoorbell Doorbell OperationCongestion Control Detailed DescriptionName Bit Transmit Source Flow Control Masks Configuration Bus Example EndiannessReset DMA ExampleReset Summary Enable and Enable Status RegistersBLK8ENSTA BLK7ENSTA Enable and Enable Status Bit Field Descriptions EnstatGblen BLK0ENBLK1EN BLK1ENSTATBLK2EN BLK2ENSTATSoftware Shutdown Details EmulationBLK8ENSTAT Peren Soft FreeEmulation Control Signals Enabling the Srio PeripheralsPeren 11.2 PLL, Ports, Device ID and Data Rate Initializations Peripheral InitializationsSet Device ID Registers Assert the Peren bit to enable logical layer data flow Read register to check portx1-4 OK bitBootload Capability ConfigurationBootload Data Movement Device WakeupMSG REQ ERRCPU Interrupts General DescriptionInterrupt Condition Control Registers Interrupt Source Configuration Options Where ICS0 Doorbell1, bit 0, through ICS15 Doorbell1, bit Interrupt Conditions LSU Interrupt Condition Clear Registers Iccr Address Offset ICS11 ICS10 ICS9 ICS8 ICS2 ICS1 ICS0ICC11 ICC10 ICC9 ICC8 ICC2 ICC1 ICC0Interrupt Condition Routing Options DOORBELL0ICRR2 Address OffsetLSUICRR1 Address Offset 0x02E4 LSUICRR2 Address Offset 0x02E8LSUICRR3 Address Offset 0x02EC Interrupt Status Decode Registers ERRRSTEVNTICRR2 Address Offset 0x02F4ERRRSTEVNTICRR3 Address Offset 0x02F8 ICR2 ICR1 ICR0Sharing of Isdr Bits Interrupt Generation Interrupt PacingISDR3 ISDR2 ISDR1 ISDR9 ISDR8 ISDR7 ISDR6 ISDR5 ISDR4 ISDR0 Interrupt Handling INTDSTnRATECNTL Interrupt Rate Control RegisterInterrupt Conditions Introduction Serial Rapid IO Srio RegistersOffset Acronym Register Description Serial Rapid IO Srio Registers Offset Acronym Register DescriptionLSUICRR3 ErrrstevnticRR2 RR3LSU3REG1 QUEUE1TXDMAC QUEUE2TXDMACQUEUE3TXDMAC QUEUE4TXDMACQUEUE12RXDMA Txcppiflowma SKS6SKS7 RxqueuetearRXUMAPL18 RXUMAPH18RXUMAPL19 RXUMAPH19Asblyid AsblyinfoPefeat SrcopSP0ERRATTRCA PTDBG0SP0ERRCAPTDB SP0ERRRATETimer SP3ERRRATESP3ERRTHRESH SpipdiscoveryPeripheral Identification Register PID Peripheral ID Register PID Field DescriptionsType Class REVPeripheral Control Register PCR Peripheral Control Register PCR Field DescriptionsPere Soft Free Bit FieldPeripheral Settings Control Register Persetcntl Cbatranspr 1XMODEPrescalerse LectENPLL3 ENPLL2ENPLL1 Peripheral Global Enable Register Gblen Peripheral Global Enable Register Gblen Field DescriptionsPeripheral Global Enable Status Register Gblenstat GBLENS TATBlock n Enable Register BLKnEN Block n Enable Register BLKnEN Field DescriptionsBlock n Enable Status Register BLKnENSTAT Block n Enable Status Register BLKnENSTATRapidIO DEVICEID1 Register DEVICEIDREG1 RapidIO DEVICEID1 Register DEVICEIDREG1 Field Descriptions8BNODEID 16BNODEIDRapidIO DEVICEID2 Register DEVICEIDREG2 RapidIO DEVICEID2 Register DEVICEIDREG2 Field DescriptionsPacket Forwarding Register n for 16b DeviceIDs PF16BCNTLn Packet Forwarding Register n for 8b DeviceIDs PF8BCNTLn CDR LOS Align Term Invpa Rate BuswidthCFGRX2219 Low Freq Gain Zero Freq at e28 min Enft Swing Invpa Rate BuswidthEntx Swing Bits DE BitsCFGTX119 Amplitude mV dfpp CFGTX1512 Amplitude ReductionSerdes Macro Configuration Register n SERDESCFGnCNTL MPY EnpllRIOCLK/RIOCLK MPYDOORBELLn Interrupt Status Register DOORBELLnICSR DOORBELLn Interrupt Status Register DOORBELLnICSRDOORBELLn Interrupt Clear Register DOORBELLnICCR DOORBELLn Interrupt Clear Register DOORBELLnICCRRX Cppi Interrupt Status Register Rxcppiicsr RX Cppi Interrupt Status Register RxcppiicsrRX Cppi Interrupt Clear Register Rxcppiiccr RX Cppi Interrupt Clear Register RxcppiiccrTX Cppi Interrupt Status Register Txcppiicsr TX Cppi Interrupt Status Register TxcppiicsrTX Cppi Interrupt Clear Register Txcppiiccr TX Cppi Interrupt Clear Register TxcppiiccrLSU Status Interrupt Register Lsuicsr LSU Status Interrupt Register Lsuicsr Field DescriptionsICS31-0 Load/Store module interrupt condition status bits LSU Clear Interrupt Register LSU Iccr LSU Clear Interrupt Register LSU Iccr Field DescriptionsICS31-0 Load/Store module interrupt clear bits 31-17 126 DOORBELLn Interrupt Condition Routing Register DOORBELLnICRR 128 RX Cppi Interrupt Condition Routing Register Rxcppi Icrr ICR RX Cppi Interrupt condition routing bitsRX Cppi Interrupt Condition Routing Register Rxcppi ICRR2 RX Cppi Interrupt Condition Routing Register Rxcppi ICRR2TX Cppi Interrupt Condition Routing Register Txcppi Icrr ICR TX Cppi Interrupt condition routing bitsTX Cppi Interrupt Condition Routing Register Txcppi ICRR2 TX Cppi Interrupt Condition Routing Register Txcppi ICRR2LSU Module Interrupt Condition Routing Register 0 LSUICRR0 ICRLSU Module Interrupt Condition Routing Register 1 LSUICRR1 LSU Module Interrupt Condition Routing Register 1 LSUICRR1LSU Module Interrupt Condition Routing Register 2 LSUICRR2 LSU Module Interrupt Condition Routing Register 2 LSUICRR2LSU Module Interrupt Condition Routing Register 3 LSUICRR3 LSU Module Interrupt Condition Routing Register 3 LSUICRR3Errrstevnticrr Errrstevnticrr Field DescriptionsERRRSTEVNTICRR2 Field Descriptions ICR11ERRRSTEVNTICRR3 ERRRSTEVNTICRR3 Field DescriptionsINTDSTn Interrupt Status Decode Registers INTDSTnDECODE INTDSTn Interrupt Status Decode Registers INTDSTnDECODEINTDSTn Interrupt Rate Control Registers INTDSTnRATECNTL CountdownvalueCountdown ValueLSUn Control Register 0 LSUnREG0 LSU n Control Register 0 LSU nREG0 Field DescriptionsAddressmsb Bit Ext address fieldsAddresslsbconfigoffset Addresslsb Configoffse TLSUn Control Register 1 LSUnREG1 LSU n Control Register 1 LSU nREG1 Field DescriptionsLSUn Control Register 2 LSUnREG2 LSU n Control Register 2 LSU nREG2 Field DescriptionsDspaddress 32b DSP byte addressLSUn Control Register 3 LSUnREG3 LSU n Control Register 3 LSU nREG3 Field DescriptionsBytecount LSUn Control Register 4 LSUnREG4 LSUn Control Register 4 LSUnREG4 Field DescriptionsLSUn Control Register 5 LSUnREG5 LSU n Control Register 5 LSU nREG5 Field DescriptionsDrbllinfo Hopcount PackettypeLSUn Control Register 6 LSUnREG6 LSUn Control Register 6 LSUnREG6 Field DescriptionsCompletioncode BSY CompletioncLSU Congestion Control Flow Mask n Lsuflowmasks n FlowmaskTxhdp Txcp Rxhdp Queue Receive DMA Completion Pointer Registers QUEUEnRXDMACP Queue Receive DMA Completion Pointer Registers QUEUEnRXDMACPTransmit Queue Teardown Register Txqueueteardown QUEUE1FLOWMASK QUEUE0FLOWMASK QUEUE3FLOWMASK QUEUE2FLOWMASKQUEUE5FLOWMASK QUEUE4FLOWMASK QUEUE7FLOWMASK QUEUE6FLOWMASKQUEUE15FLOWMASK QUEUE14FLOWMASK MaskReceive Queue Teardown Register Rxqueueteardown Receive Queue Teardown Register RxqueueteardownReceive Cppi Control Register Rxcppicntl Receive Cppi Control Register Rxcppicntl Field DescriptionsTxqueuemap 3NUMMSGS3QUEUEPTR 2NUMMSGS7NUMMSGS 7QUEUEPTR6NUMMSGS 6QUEUEPTR11NUMMSGS 11QUEUEPTR10NUMMSGS 10QUEUEPTR15NUMMSGS 15QUEUEPTR14NUMMSGS 14QUEUEPTRMailbox-to-Queue Mapping Register Ln RXUMAPLn Mailbox-to-Queue Mapping Register Hn RXUMAPHn Flow Control Table Entry Registers FLOWCNTLn FlowcntlidDevice Identity CAR Devid Device Identity CAR Devid Field DescriptionsDevice Information CAR Devinfo Device Information CAR Devinfo Field DescriptionsDevicerev Vendor supply device revisionAssembly Identity CAR Asblyid Assembly Identity CAR Asblyid Field DescriptionsAssembly Information CAR Asblyinfo Assembly Information CAR Asblyinfo Field DescriptionsProcessing Element Features CAR Pefeat Processing Element Features CAR Pefeat Field DescriptionsSource Operations CAR Srcop Source Operations CAR Srcop Field DescriptionsDestination Operations CAR Destop Destination Operations CAR Destop Field DescriptionsProcessing Element Logical Layer Control CSR Pellctl ExtendedaddressIngcontrol RessingcontLocal Configuration Space Base Address 0 CSR Lclcfghbar LcsbaLocal Configuration Space Base Address 1 CSR Lclcfgbar Local Configuration Space Base Address 1 CSR LclcfgbarBase Device ID CSR Baseid Base Device ID CSR Baseid Field DescriptionsHost Base Device ID Lock CSR Hostbaseidlock HostbasedeviceidHostbasede ViceidComponent Tag CSR Comptag Component Tag CSR Comptag Field DescriptionsComponenttag Efptr EfidPort Link Timeout Control CSR Spltctl Field Descriptions Port Link Time-Out Control CSR SpltctlPort Response Time-Out Control CSR Sprtctl Port Response Time-Out Control CSR SprtctlPort General Control CSR Spgenctl Port General Control CSR Spgenctl Field DescriptionsPort Link Maintenance Request CSR n SPnLMREQ CommandPort Link Maintenance Response CSR n SPnLMRESP Port Local AckID Status CSR n SPnACKIDSTAT Port Error and Status CSR n SPnERRSTAT Port Error and Status CSR n SPnERRSTAT Field DescriptionsPortok PortuninitiaLized Port Control CSR n SPnCTL Port Control CSR n SPnCTL Field DescriptionsPort Control CSR n SP nCTL Field Descriptions NableError Reporting Block Header Errrptbh Error Reporting Block Header Errrptbh Field DescriptionsLogical/Transport Layer Error Detect CSR Errdet Logical/Transport Layer Error Enable CSR Erren Logical/Transport Layer High Address Capture CSR Haddrcapt ADDRESS633250 bit addresses Logical/Transport Layer Address Capture CSR Addrcapt ADDRESS313Xamsbs Logical/Transport Layer Device ID Capture CSR Idcapt Msbdestid DestidMsbsourceid Sourceid MsbdestidLogical/Transport Layer Control Capture CSR Ctrlcapt Ftype Ttype MsginfoImpspecific FtypePort-Write Target Device ID CSR Pwtgtid Port-Write Target Device ID CSR Pwtgtid Field DescriptionsDeviceidmsb DeviceidPort Error Detect CSR n SPnERRDET Port Error Detect CSR n SPnERRDET Field DescriptionsPort Error Rate Enable CSR n SPnRATEEN Port Error Rate Enable CSR n SPnRATEEN Field DescriptionsPort n Attributes Error Capture CSR 0 SPnERRATTRCAPTDBG0 CAPTURE0 CAPTURE0CAPTURE1 CAPTURE1CAPTURE2 CAPTURE2CAPTURE3 CAPTURE3Port Error Rate CSR n SPnERRRATE Port Error Rate CSR n SPnERRRATE Field DescriptionsPort Error Rate Threshold CSR n SPnERRTHRESH Port IP Discovery Timer in 4x mode Spipdiscoverytimer DiscoverytimerPwtimer DiscoverytiPort IP Mode CSR Spipmode Port IP Mode CSR Spipmode Field DescriptionsPort IP Mode CSR Spipmode Field Descriptions RstenSerial Port IP Prescalar Ipprescal Serial Port IP Prescalar Ipprescal Field DescriptionsPrescale Port-Write-In Capture CSR n SPIPPWINCAPTn PwcaptPort Reset Option CSR n SPnRSTOPT Port Reset Option CSR n SP nRSTOPT Field DescriptionsPortid Port Control Independent Register n SPnCTLINDEP Maxretryen MaxretryerMaxretryth IrqenPort Silence Timer n SPnSILENCETIMER Port Silence Timer n SPnSILENCETIMER Field DescriptionsSilencetimer Multevntcs MultevntcsPort Control Symbol Transmit n SPnCSTX Port Control Symbol Transmit n SP nCSTX Field DescriptionsImportant Notice
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