Texas Instruments TMS320C645x manual Queue Mapping Register Rxumapl n, Bit Name Description

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SRIO Functional Description

 

 

 

Figure 17. Queue Mapping Register RXU_MAP_Ln

 

 

31

30

29

 

 

24

23

22

21

 

 

16

Letter Mask

 

Mailbox Mask

 

 

Letter

 

 

Mailbox

 

 

R/W-11

 

R/W-111111

 

 

R/W-0

 

 

R/W-000000

 

 

15

 

 

 

 

 

 

 

 

 

 

0

 

 

 

 

 

SOURCEID

 

 

 

 

 

 

 

 

 

 

R/W-0x0000

 

 

 

 

 

LEGEND: R = Read, W = Write, n = value at reset

 

 

 

 

 

 

 

 

 

 

 

Figure 18. Queue Mapping Register RXU_MAP_Hn

 

 

31

 

 

 

 

 

 

 

 

 

 

16

 

 

 

 

 

Reserved

 

 

 

 

 

 

 

 

 

 

 

R-0

 

 

 

 

 

15

 

 

10

9

8

7

6

5

2

1

0

 

 

Reserved

 

 

tt

Reserved

 

QueueID

Promis

Segme

 

 

 

 

 

 

 

 

 

 

cuous

nt

 

 

 

 

 

 

 

 

 

 

 

Mappi

 

 

 

 

 

 

 

 

 

 

 

ng

 

 

R-0

 

 

R/W-01

R-00

 

 

R/W-0000

R/W-0

R/W-0

LEGEND: R = Read, W = Write, n = value at reset

 

 

 

 

 

 

 

 

The packet manager maintains the RX DMA state of free and used data buffers within the memory space. It directs the data to specific addresses within the memory and maintains and updates the buffer descriptor queues. There is a single buffer descriptor per RapidIO message. For example, single segment messages have one buffer descriptor, as do multi-segment messages with up to 4KB payloads.

There can be multiple RX buffer descriptor queues per core. It is suggested that one queue be dedicated to single segment messages and additional queues be dedicated to multi-segment messages. Each multi-segment message queue can support only one incoming message at a time. Depending on the application, it may be necessary to support multiple simultaneous SAR operations per core. In this case, a buffer descriptor queue is allocated for each desired simultaneous message. The peripheral supports a total of 16 assignable RX queues and their associated RX DMA state registers. Each of the queues can be assigned to single or multi-segment messages.

Table 15 and Table 16 show the RX DMA State Registers.

Table 15. RX DMA State Head Descriptor Pointer (HDP) (Address Offset 0x600-0x63C)

Bit

Name

Description

31:0

RX Queue Head

Rx Queue Head Descriptor Pointer: This field is the host memory address for the first buffer

 

Descriptor Pointer

descriptor in the channel receive queue. This field is written by the host to initiate queue receive

 

 

operations and is zeroed by the port when all free buffers have been used. An error condition

 

 

results if the host writes this field when the current field value is nonzero. The address must be

 

 

32-bit word aligned.

Table 16. RX DMA State Completion Pointer (CP) (Address Offset 0x600-0x63C)

Bit

Name

Description

31:0

RX Queue

Rx Queue Completion Pointer: This field is the host memory address for the receive queue

 

Completion Pointer

completion pointer. This register is written by the host with the buffer descriptor address for the last

 

 

buffer processed by the host during interrupt processing. The port uses the value written to

 

 

determine if the interrupt should be deasserted.

SPRU976 –March 2006

Serial RapidIO (SRIO)

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Contents Users Guide Submit Documentation Feedback Contents Errrstevnticrr Base Device ID CSR Baseid List of Figures Load/Store Module Interrupt Condition Routing Registers 150 Port Error Rate Threshold CSR n SP n Errthresh List of Tables LSUn Control Register 0 LSUnREG0 Field Descriptions Base Device ID CSR Baseid Field Descriptions Read This First RapidIO Architectural Hierarchy General RapidIO SystemOverview 3 1x/4x LP-Serial RapidIO Interconnect ArchitectureFeatures Supported in Srio RapidIO Feature Support in SrioRapidIO Documents and Links Features Not SupportedStandards External Devices RequirementsPeripheral Data Flow OverviewOperation Sequence Srio PacketsExample Packet Streaming Write Operation Sequence4x RapidIO Packet Data Stream Streaming-Write Class Control SymbolsPacket Type Srio Packet Ftype/TtypeFtype Ttype Packet Type Pin Description Srio PinsBlock Diagram Functional OperationSrio Conceptual Block Diagram Bit Name Value Description Serdes and its ConfigurationsEnabling the PLL Bits of Serdescfg nCNTL Register 0x120 0x12cLine Rate versus PLL Output Clock Frequency Bits of Serdescfg nCNTL Register 0x120 0x12cRate Bit Effects Enabling the Receiver Frequency Range versus MPYBits of Serdescfgrx nCNTL Registers Bits of SERDESCFGRXnCNTL Registers Disabled. Loss of signal detection disabledBit Field Value Description 1514 CFGRX2219 Low Freq Gain EQ BitsEnabling the Transmitter Bits of Serdescfgtx nCNTL RegistersSwing Bits Bits of Serdescfgtx nCNTL RegistersDE Bits DirectIO Serdes Configuration ExampleRapidIO Packet Header Field Control/Command Register Field MappingBSY Control/Command Register RapidIO Packet Header FieldStatus Fields Status Field FunctionLSU Registers Timing Detailed Data Path Description Example Burst NwriterWrite Transactions TX OperationRead Transactions RX Operation SegmentationMessage Passing Reset and Power Down StateCppi RX Scheme for RapidIO Queue Mapping Table Address Offset 0x0800 0x08FC Bit Name Description Queue Mapping Register Rxumapl nRX Buffer Descriptor Fields Field Description RX Buffer Descriptor Field DescriptionsField Description RX Buffer Descriptor Field DescriptionsRX Cppi Mode Explanation Cppi Boundary Diagram TX Buffer Descriptor Field Definitions TX Buffer Descriptor FieldsUses this bit to reclaim buffers Ssize TXQUEUECNTL2- Address Offset 0x7E8 Name Bit Access Reset Value DescriptionTXQUEUECNTL0- Address Offset 0x7E0 TXQUEUECNTL1- Address Offset 0x7E4TXQueueMap10 2316 0x0A Detailed Data Path Description RX Operation Message Passing Software RequirementsTX Operation Queue Mapping Initialization ExampleRX Buffer Descriptor NDP TX Buffer DescriptorStart Message Passing MaintenanceDoorbell Operation DoorbellDetailed Description Congestion ControlName Bit Transmit Source Flow Control Masks Endianness Configuration Bus ExampleDMA Example ResetEnable and Enable Status Registers Reset SummaryBLK8ENSTA BLK7ENSTA BLK0EN Enable and Enable Status Bit Field DescriptionsEnstat GblenBLK2ENSTAT BLK1ENBLK1ENSTAT BLK2ENPeren Soft Free Software Shutdown DetailsEmulation BLK8ENSTATEnabling the Srio Peripherals Emulation Control SignalsPeren Peripheral Initializations 11.2 PLL, Ports, Device ID and Data Rate InitializationsSet Device ID Registers Read register to check portx1-4 OK bit Assert the Peren bit to enable logical layer data flowDevice Wakeup Bootload CapabilityConfiguration Bootload Data MovementERR MSG REQGeneral Description CPU InterruptsInterrupt Condition Control Registers Interrupt Source Configuration Options Where ICS0 Doorbell1, bit 0, through ICS15 Doorbell1, bit Interrupt Conditions LSU Interrupt Condition Clear Registers Iccr Address Offset ICC2 ICC1 ICC0 ICS11 ICS10 ICS9 ICS8ICS2 ICS1 ICS0 ICC11 ICC10 ICC9 ICC8DOORBELL0ICRR2 Address Offset Interrupt Condition Routing OptionsLSUICRR2 Address Offset 0x02E8 LSUICRR1 Address Offset 0x02E4LSUICRR3 Address Offset 0x02EC ICR2 ICR1 ICR0 Interrupt Status Decode RegistersERRRSTEVNTICRR2 Address Offset 0x02F4 ERRRSTEVNTICRR3 Address Offset 0x02F8Sharing of Isdr Bits Interrupt Pacing Interrupt GenerationISDR3 ISDR2 ISDR1 ISDR9 ISDR8 ISDR7 ISDR6 ISDR5 ISDR4 ISDR0 INTDSTnRATECNTL Interrupt Rate Control Register Interrupt HandlingInterrupt Conditions Serial Rapid IO Srio Registers IntroductionOffset Acronym Register Description Offset Acronym Register Description Serial Rapid IO Srio RegistersRR3 LSUICRR3Errrstevntic RR2LSU3REG1 QUEUE4TXDMAC QUEUE1TXDMACQUEUE2TXDMAC QUEUE3TXDMACQUEUE12RXDMA Rxqueuetear TxcppiflowmaSKS6 SKS7RXUMAPH19 RXUMAPL18RXUMAPH18 RXUMAPL19Srcop AsblyidAsblyinfo PefeatSP0ERRRATE SP0ERRATTRCAPTDBG0 SP0ERRCAPTDBSpipdiscovery TimerSP3ERRRATE SP3ERRTHRESHClass REV Peripheral Identification Register PIDPeripheral ID Register PID Field Descriptions TypeBit Field Peripheral Control Register PCRPeripheral Control Register PCR Field Descriptions Pere Soft FreePeripheral Settings Control Register Persetcntl Lect Cbatranspr1XMODE PrescalerseENPLL2 ENPLL3ENPLL1 Peripheral Global Enable Register Gblen Field Descriptions Peripheral Global Enable Register GblenTAT Peripheral Global Enable Status Register GblenstatGBL ENSBlock n Enable Register BLKnEN Field Descriptions Block n Enable Register BLKnENBlock n Enable Status Register BLKnENSTAT Block n Enable Status Register BLKnENSTAT16BNODEID RapidIO DEVICEID1 Register DEVICEIDREG1RapidIO DEVICEID1 Register DEVICEIDREG1 Field Descriptions 8BNODEIDRapidIO DEVICEID2 Register DEVICEIDREG2 Field Descriptions RapidIO DEVICEID2 Register DEVICEIDREG2Packet Forwarding Register n for 16b DeviceIDs PF16BCNTLn Packet Forwarding Register n for 8b DeviceIDs PF8BCNTLn Term Invpa Rate Buswidth CDR LOS AlignCFGRX2219 Low Freq Gain Zero Freq at e28 min Swing Invpa Rate Buswidth EnftEntx CFGTX1512 Amplitude Reduction Swing BitsDE Bits CFGTX119 Amplitude mV dfppMPY Serdes Macro Configuration Register n SERDESCFGnCNTLMPY Enpll RIOCLK/RIOCLKDOORBELLn Interrupt Status Register DOORBELLnICSR DOORBELLn Interrupt Status Register DOORBELLnICSRDOORBELLn Interrupt Clear Register DOORBELLnICCR DOORBELLn Interrupt Clear Register DOORBELLnICCRRX Cppi Interrupt Status Register Rxcppiicsr RX Cppi Interrupt Status Register RxcppiicsrRX Cppi Interrupt Clear Register Rxcppiiccr RX Cppi Interrupt Clear Register RxcppiiccrTX Cppi Interrupt Status Register Txcppiicsr TX Cppi Interrupt Status Register TxcppiicsrTX Cppi Interrupt Clear Register Txcppiiccr TX Cppi Interrupt Clear Register TxcppiiccrLSU Status Interrupt Register Lsuicsr Field Descriptions LSU Status Interrupt Register LsuicsrICS31-0 Load/Store module interrupt condition status bits LSU Clear Interrupt Register LSU Iccr Field Descriptions LSU Clear Interrupt Register LSU IccrICS31-0 Load/Store module interrupt clear bits 31-17 126 DOORBELLn Interrupt Condition Routing Register DOORBELLnICRR 128 ICR RX Cppi Interrupt condition routing bits RX Cppi Interrupt Condition Routing Register Rxcppi IcrrRX Cppi Interrupt Condition Routing Register Rxcppi ICRR2 RX Cppi Interrupt Condition Routing Register Rxcppi ICRR2ICR TX Cppi Interrupt condition routing bits TX Cppi Interrupt Condition Routing Register Txcppi IcrrTX Cppi Interrupt Condition Routing Register Txcppi ICRR2 TX Cppi Interrupt Condition Routing Register Txcppi ICRR2ICR LSU Module Interrupt Condition Routing Register 0 LSUICRR0LSU Module Interrupt Condition Routing Register 1 LSUICRR1 LSU Module Interrupt Condition Routing Register 1 LSUICRR1LSU Module Interrupt Condition Routing Register 2 LSUICRR2 LSU Module Interrupt Condition Routing Register 2 LSUICRR2LSU Module Interrupt Condition Routing Register 3 LSUICRR3 LSU Module Interrupt Condition Routing Register 3 LSUICRR3Errrstevnticrr Field Descriptions ErrrstevnticrrICR11 ERRRSTEVNTICRR2 Field DescriptionsERRRSTEVNTICRR3 Field Descriptions ERRRSTEVNTICRR3INTDSTn Interrupt Status Decode Registers INTDSTnDECODE INTDSTn Interrupt Status Decode Registers INTDSTnDECODEValue INTDSTn Interrupt Rate Control Registers INTDSTnRATECNTLCountdownvalue CountdownBit Ext address fields LSUn Control Register 0 LSUnREG0LSU n Control Register 0 LSU nREG0 Field Descriptions AddressmsbLSU n Control Register 1 LSU nREG1 Field Descriptions AddresslsbconfigoffsetAddresslsb Configoffse T LSUn Control Register 1 LSUnREG132b DSP byte address LSUn Control Register 2 LSUnREG2LSU n Control Register 2 LSU nREG2 Field Descriptions DspaddressLSU n Control Register 3 LSU nREG3 Field Descriptions LSUn Control Register 3 LSUnREG3Bytecount LSUn Control Register 4 LSUnREG4 Field Descriptions LSUn Control Register 4 LSUnREG4Hopcount Packettype LSUn Control Register 5 LSUnREG5LSU n Control Register 5 LSU nREG5 Field Descriptions DrbllinfoCompletionc LSUn Control Register 6 LSUnREG6LSUn Control Register 6 LSUnREG6 Field Descriptions Completioncode BSYFlowmask LSU Congestion Control Flow Mask n Lsuflowmasks nTxhdp Txcp Rxhdp Queue Receive DMA Completion Pointer Registers QUEUEnRXDMACP Queue Receive DMA Completion Pointer Registers QUEUEnRXDMACPTransmit Queue Teardown Register Txqueueteardown QUEUE7FLOWMASK QUEUE6FLOWMASK QUEUE1FLOWMASK QUEUE0FLOWMASKQUEUE3FLOWMASK QUEUE2FLOWMASK QUEUE5FLOWMASK QUEUE4FLOWMASKMask QUEUE15FLOWMASK QUEUE14FLOWMASKReceive Queue Teardown Register Rxqueueteardown Receive Queue Teardown Register RxqueueteardownReceive Cppi Control Register Rxcppicntl Field Descriptions Receive Cppi Control Register Rxcppicntl2NUMMSGS Txqueuemap3NUMMSGS 3QUEUEPTR6QUEUEPTR 7NUMMSGS7QUEUEPTR 6NUMMSGS10QUEUEPTR 11NUMMSGS11QUEUEPTR 10NUMMSGS14QUEUEPTR 15NUMMSGS15QUEUEPTR 14NUMMSGSMailbox-to-Queue Mapping Register Ln RXUMAPLn Mailbox-to-Queue Mapping Register Hn RXUMAPHn Flowcntlid Flow Control Table Entry Registers FLOWCNTLnDevice Identity CAR Devid Field Descriptions Device Identity CAR DevidVendor supply device revision Device Information CAR DevinfoDevice Information CAR Devinfo Field Descriptions DevicerevAssembly Identity CAR Asblyid Field Descriptions Assembly Identity CAR AsblyidAssembly Information CAR Asblyinfo Field Descriptions Assembly Information CAR AsblyinfoProcessing Element Features CAR Pefeat Field Descriptions Processing Element Features CAR PefeatSource Operations CAR Srcop Field Descriptions Source Operations CAR SrcopDestination Operations CAR Destop Field Descriptions Destination Operations CAR DestopRessingcont Processing Element Logical Layer Control CSR PellctlExtendedaddress IngcontrolLcsba Local Configuration Space Base Address 0 CSR LclcfghbarLocal Configuration Space Base Address 1 CSR Lclcfgbar Local Configuration Space Base Address 1 CSR LclcfgbarBase Device ID CSR Baseid Field Descriptions Base Device ID CSR BaseidViceid Host Base Device ID Lock CSR HostbaseidlockHostbasedeviceid HostbasedeComponent Tag CSR Comptag Field Descriptions Component Tag CSR ComptagComponenttag Efid EfptrPort Link Time-Out Control CSR Spltctl Port Link Timeout Control CSR Spltctl Field DescriptionsPort Response Time-Out Control CSR Sprtctl Port Response Time-Out Control CSR SprtctlPort General Control CSR Spgenctl Field Descriptions Port General Control CSR SpgenctlCommand Port Link Maintenance Request CSR n SPnLMREQPort Link Maintenance Response CSR n SPnLMRESP Port Local AckID Status CSR n SPnACKIDSTAT Port Error and Status CSR n SPnERRSTAT Field Descriptions Port Error and Status CSR n SPnERRSTATPortuninitia PortokLized Port Control CSR n SPnCTL Field Descriptions Port Control CSR n SPnCTLNable Port Control CSR n SP nCTL Field DescriptionsError Reporting Block Header Errrptbh Field Descriptions Error Reporting Block Header ErrrptbhLogical/Transport Layer Error Detect CSR Errdet Logical/Transport Layer Error Enable CSR Erren ADDRESS6332 Logical/Transport Layer High Address Capture CSR Haddrcapt50 bit addresses ADDRESS313 Logical/Transport Layer Address Capture CSR AddrcaptXamsbs Msbdestid Logical/Transport Layer Device ID Capture CSR IdcaptMsbdestid Destid Msbsourceid SourceidFtype Logical/Transport Layer Control Capture CSR CtrlcaptFtype Ttype Msginfo ImpspecificDeviceid Port-Write Target Device ID CSR PwtgtidPort-Write Target Device ID CSR Pwtgtid Field Descriptions DeviceidmsbPort Error Detect CSR n SPnERRDET Field Descriptions Port Error Detect CSR n SPnERRDETPort Error Rate Enable CSR n SPnRATEEN Field Descriptions Port Error Rate Enable CSR n SPnRATEENPort n Attributes Error Capture CSR 0 SPnERRATTRCAPTDBG0 CAPTURE0 CAPTURE0CAPTURE1 CAPTURE1CAPTURE2 CAPTURE2CAPTURE3 CAPTURE3Port Error Rate CSR n SPnERRRATE Field Descriptions Port Error Rate CSR n SPnERRRATEPort Error Rate Threshold CSR n SPnERRTHRESH Discoveryti Port IP Discovery Timer in 4x mode SpipdiscoverytimerDiscoverytimer PwtimerPort IP Mode CSR Spipmode Field Descriptions Port IP Mode CSR SpipmodeRsten Port IP Mode CSR Spipmode Field DescriptionsSerial Port IP Prescalar Ipprescal Field Descriptions Serial Port IP Prescalar IpprescalPrescale Pwcapt Port-Write-In Capture CSR n SPIPPWINCAPTnPort Reset Option CSR n SP nRSTOPT Field Descriptions Port Reset Option CSR n SPnRSTOPTPortid Port Control Independent Register n SPnCTLINDEP Irqen MaxretryenMaxretryer MaxretrythPort Silence Timer n SPnSILENCETIMER Field Descriptions Port Silence Timer n SPnSILENCETIMERSilencetimer Multevntcs MultevntcsPort Control Symbol Transmit n SP nCSTX Field Descriptions Port Control Symbol Transmit n SPnCSTXImportant Notice
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