Using EZ-KIT Lite
External Memory
The
Table
Table
Start Address | End Address | Content | ||
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0x0020 | 0000 | 0x0027 | FFFF | SRAM memory (~MS0) |
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0x0400 | 0000 | 0x040F FFFF | Flash memory (~MS1) | |
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0x0800 | 0000 | 0x08FF 0000 | SDRAM memory (~MS2) | |
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0x0C00 0000 | 0x0CFF FFFF | Unused chip select (~MS3), for | ||
0x0C00 0000 | 0x0FFF FFFF | Unused chip select (~MS3), for SDRAM addresses | ||
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The parallel flash memory, SDRAM, and SRAM memory connect to the external memory of the processor. To access the SRAM and flash memo- ries, use memory addressing via the respective memory bank or use the DMA controller.
The SDRAM memory connects to the SDRAM controller of the proces- sor. A set of programmable timing parameters is available to configure the SDRAM banks to support slower memory accesses. Care must be taken when configuring the SDRAM control registers. For more information regarding the setup of the SDRAM controller, please refer to the