Rosemount 848L, Reference Manual

Reference Manual

00809-0100-4696, Rev AA September 2004

Rosemount 848L

Table D-1. Supported Functions

	Required number	Maximum number		Maximum
Function Name	of parameters	of parameters	Function Description	Instances

PS	2	2	PS (channel number, divisor);	10
			This function is a frequency prescaler. This function's
			value will be true for 1 execution cycle each time the
			requested device input has had 'divisor' pulses. This is
			ideal for a scaling fast pulse inputs to a rate suitable for
			the logic execution cycle.

RISE	1	1	RISE (a);	10
			This function is a rising edge trigger. When 'a'
			transitions from false to true, this function's result is
			true, otherwise it is false.
RS	2	2	RS (set, reset);	10
			This function is a reset dominant latch. When 'reset' is
			true, this function will reset its' state to false regardless
			of the value of 'set'. When 'reset' is false, the function's
			state will have a false value until 'set' has had at least 1
			true reading, after which the state will remain true. The
			result of this function is the function's state.

SHL	3	4	SHL (a, clock, reset, bit);	10
			This function is an 8 bit left shift register. When 'clock'
			transitions from false to true, the value of 'a' is shifted
			into the least significant bit of this function's register.
			The remaining bits are shifted left by 1 bit position.
			When 'reset' is true, all 8 bits in this function's register
			will be cleared to zero. 'reset' is an optional parameter
			and will always be considered false if it is not present.
			The result of this function is the value of bit number 'bit'
			in the register.
SHR	3	4	SHR (a, clock, reset, bit);	10
			This function is an 8 bit right shift register. When 'clock'
			transitions from false to true, the value of 'a' is shifted
			into the most significant bit of this function's register.
			The remaining bits are shifted right by 1 bit position.
			When 'reset' is true, all 8 bits in this function's register
			will be cleared to zero. 'reset' is an optional parameter
			and will always be considered false if it is not present.
			The result of this function is the value of bit number 'bit'
			in the register.

SR	2	2	SR (set, reset);	10
			This function is a set dominant latch. When 'set' is true,
			this function will set its' state to true regardless of the
			value of 'reset'. When 'reset' is false, the function's state
			will have a false value until 'set' has had at least 1 true
			reading, after which the state will remain true. When
			reset is true, the function's state will be set to the value
			of 'set'. The result of this function is the function's state.
TOF	2	2	TOF (a, time);	10
			This function is an off delay. When 'a' is true, this

function will set its' output to true. When 'a' transitions to false, the function's output will remain true for 'time' * 100 milliseconds before going false.

D-3

PS (channel number, divisor);