Texas Instruments SLAU081 Adccs, Dspdx Evmclkx, Adctc Sysclk, Start Dspfsx, SAM Dspdx, Dspfsx SAM

Page 40

1

2

3

5(9

5HYLVLRQ4

+LVWRU\

$SSURYHG

U16B

+DVdd

U13A

(&11XPEHU

DSP_DR

DSP_DR

17

I12/O0/Q0

I11

16

14

28

GND

Vcc

MOM

ADC_Data_n3

18

I13/O1/Q1

I10

13

C63

D

0.1uF

LCL_CS_ADC*

ADC_CS*

19

I14/O2/Q2

I9

12

ADC_Data_out

MOM

MOM

D

DAC_Data_in

DAC_Data_in 20

I15/O3/Q3

I8

11

DSP_DX

EVM_CLKX

EVM_CLKX

TP15

21

I16/O4/Q4

I7

10

ADC_TC*

SYSCLK

SYSCLK

U13B

Q0

START*

DSP_FSX

+DVdd

23

I17/O5/Q5

I6

9

DSP_FSX

14

GND

Vcc

28

Q1

24

I18/O6/Q6

I5

7

SAM*

DSP_DX

DSP_DX

C55

Q2

25

I19/O7/Q7

I4

6

DAC_Type

DSP_XF

DSP_XF

0.1uF

+DVdd

Q3

DSP_FSX

SAM*

26

I20/O8/Q8

I3

5

SAM*

INIT*

27

I21/O9/Q9

I2

4

DSP_XF

DAC_Type

DAC_Type

R39

U14B

10K

RESET

ADC_Data_out

+DVdd

I1

3

ADC_Data_out

TP14

14

28

1

2

SYSCLK

START*

GND

Vcc

NC

CLK/I0

C

8

C

C54

NC

15

NC

0.1uF

22

START

NC

SW2

+DVdd

U16A

U14A

U10

RESET

R42

3

OUT

RESET

4

17

16

ADC_TC*

17

16

10K

FS

I12/O0/Q0

I11

I12/O0/Q0

I11

TP19

18

13

Q0

18

13

Q0

+DVdd

7

I13/O1/Q1

I10

I13/O1/Q1

I10

DISCH

LCL_CS_DAC*

19

I14/O2/Q2

I9

12

Q1

19

I14/O2/Q2

I9

12

Q1

8

VCC

C61

6

R41

Q2

Q2

THRES

20

11

20

11

5

LCL_CLKX

I15/O3/Q3

I8

I15/O3/Q3

I8

C60

CONT

10K

ADC_Data_n3

21

I16/O4/Q4

I7

10

Q3

21

I16/O4/Q4

I7

10

Q3

0.1uF

B

TRIG

2

B

MOM

C62

23

9

23

9

1

I17/O5/Q5

I6

I17/O5/Q5

I6

GND

24

I18/O6/Q6

I5

7

DAC_Type

24

I18/O6/Q6

I5

7

DAC_Type

NE555D

RESET

25

I19/O7/Q7

I4

6

EVM_CLKX

25

I19/O7/Q7

I4

6

INIT*

SW3

ADC_Data_out

26

I20/O8/Q8

I3

5

DSP_FSX

26

I20/O8/Q8

I3

5

DSP_FSX

TP17

27

4

DSP_XF

27

4

DSP_XF

I21/O9/Q9

I2

I21/O9/Q9

I2

I1

3

RESET

I1

3

RESET

1

NC

CLK/I0

2

SYSCLK

1

NC

CLK/I0

2

SYSCLK

8

8

NC

NC

15

15

NC

NC

22

22

NC

NC

A

12500 TI Boulevard. Dallas, Texas 75243

A

TITLE:

Stand Alone

DAC_Write*

Engineer:

Joe Purvis

DOCUMENT CONTROL #:

REV:

Drawn By:

Joe Purvis

6430333

FILE:

Stand Alone Mode

DATE:

28-Nov-2001

SIZE: A4

SHEET:

10

OF:

14

1

2

3

4

Image 40

Contents User’s Guide Important Notice EVM Important Notice EVM Warnings and Restrictions Contents Figures Introduction Stand-Alone Mode SAM EVM ModesStand-Alone Mode User ModeAnalog Input Conditioning Analog Output ConditioningGetting Started Shipping Default Configuration SAM ConfigurationSwitch Settings Default Description ConfigurationJumper Settings Default Configuration DescriptionJumpers Analog I/O Signal ConditioningChannel 0 Analog Input Signal Generator Channel 0 Analog OutputVoltage Reference ADC Supply VoltageClock/Timer Routing SwitchesStand-Alone-Mode, SW1-1 Reference Description Pin Function Designator Number ConnectorsEvaluation board, SIL Agnd EVM power Analog output option No output Pin DIL header Evaluation board, SIL Reference Description Pin Signal Designator Number ADC and DAC Direct AccessHost Communication Common Connector FSX Host Connector Pin No Signal Legacy ConnectorEVM Connector J13 Pin No Signal J13 Host Connector Plugged into J12 J15 Pin No Signal J13 Pin No Signal Pin No SignalJ13 J13 Wire Wrap J15 Wire Wrap J13 JumperAll of these connectors are shown below Description Pin Signal Name/Function Designator Number Pin connector J12 pin Bill of Materials, Board Layout, and Schematics BNC0 Dspclks DspxfDspclkx DspclkrFL2 +VS +VINGND FL3 RefinFB3 BLM11A121SGPB+VIN TP9 FB2 ENA OUTGND RV7 RV9Trim Agnd VDD SDODacout OUT/OUTB AOUTW19 AOUTAW15A2FLT A2OUTRV8 OutaDacout Clkx ClkrFB5 FSX BLM11A121SGPB FB4 FSRDsptout Sysclk Dspclks EvmclkxDspclkx Dspfsr Dspclkr DsptoutReset AdccsDspdx Evmclkx Adctc SysclkTP7 TP6TP5 RV3U4A RV4TP1 TP2 TP3 TP4 PT1RV2 RV1