Cypress CY14B108L manuals
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24 pages 862.73 Kb
PRELIMINARY CY14B108L, CY14B108N 8 Mbit (1024K x 8/512K x 16) nvSRAMFeatures20 ns, 25 ns, and 45 ns Access Times Internally organized as 1024K x 8 (CY14B108L) or 512K x 16 (CY14B108N)Hands off Automatic STORE on power down with only a small CapacitorSTORE to QuantumTrap nonvolatile elements initiated by Software, device pin, or AutoStore on power down Functional Description Logic Block DiagramDocument #: 001-45523 Rev. *B Page 2 of 24 2 Pinouts (x16) HSB WE 43 41 40 39 38 37 36 35 34 33 31 30 29 28 27 26 25 22 23 CE Top View (not to scale)B 3 HSB WE Figure 1. Pin Diagram - 48 FBGA Figure 2. Pin Diagram - 44/54-Pin TSOP IICE OE NC DQ 26 5 4 1 D E C F G H 48-FBGA(x8) CE OE NC BLE 26 5 4 1 D E C F G H 48-FBGA(x16) (not to scale)Notes 4. Address expansion for 16 Mbit. NC pin not connected to die. OE 2 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 44 Top View (not to scale) 54-TSOP II 44-TSOP II(x8) Top View (not to scale) 4 PRELIMINARY CY14B108L, CY14B108N8 PRELIMINARY CY14B108L, CY14B108NMaximum Ratings Operating Range DC Electrical Characteristics 9 AC Test ConditionsData Retention and Endurance Capacitance Thermal Resistance 10 PRELIMINARY CY14B108L, CY14B108NAC Switching Characteristics Switching Waveforms 11 Figure 6. SRAM Read Cycle #2: CE and OE Controlled[3, 11, 15]Figure 7. SRAM Write Cycle #1: WE Controlled[3, 14, 15, 16] 12 Figure 8. SRAM Write Cycle #2: CE Controlled[3, 14, 15, 16]Figure 9. SRAM Write Cycle #3: BHE and BLE Controlled[3, 14, 15, 16] 13 AutoStore/Power Up RECALLFigure 10. AutoStore or Power Up RECALL 14 PRELIMINARY CY14B108L, CY14B108NSoftware Controlled STORE/RECALL CycleFigure 11. CE and OE Controlled Software STORE/RECALL Cycle[23] Figure 12. Autostore Enable/Disable Cycle Hardware STORE CycleFigure 13. Hardware STORE Cycle[18] Figure 14. Soft Sequence Processing 15 Write latch setWrite latch not set 24 PRELIMINARY CY14B108L, CY14B108NSales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions
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