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Cypress manual Preliminary, CY14B108L, CY14B108N, SRAM Read Cycle #2 CE and OE Controlled3, 11

Models: CY14B108N CY14B108L

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PRELIMINARY	CY14B108L, CY14B108N

Figure 6. SRAM Read Cycle #2: CE and OE Controlled[3, 11, 15]

Address

Address Valid

		tRC	tHZCE
CE		tACE
CE
		tAA
		tLZCE	t
			HZOE
OE		tDOE
OE
		tLZOE	tHZBE
		tDBE
BHE, BLE
		tLZBE
Data Output	High Impedance		Output Data Valid
Data Output		tPU	Output Data Valid
		tPU	tPD
			tPD
ICC	Standby	Active

Figure 7. SRAM Write Cycle #1: WE Controlled[3, 14, 15, 16]

		W:&
$GGUHVV		$GGUHVV9DOLG
		W6&(	W+$
&(
		W%:
%+(%/(
		W$:
		W3:(
:(		W6$
		W6$
		W6'	W+'
'DWD,QSXW			,QSXW'DWD9DOLG
		W+=:(	W/=:(
'DWD2XWSXW	3UHYLRXV'DWD	+LJK,PSHGDQFH
'DWD2XWSXW	3UHYLRXV'DWD

Notes

16. CE or WE must be >VIH during address transitions.

Document #: 001-45523 Rev. *B

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Cypress manual Preliminary, CY14B108L, CY14B108N, SRAM Read Cycle #2 CE and OE Controlled3, 11, + Feedback

Contents

CY14B108L, CY14B108N FeaturesLogic Block Diagram1 PRELIMINARYnot to scale Pinouts12 Top View 13 not to scale Top ViewTable 1. Pin Definitions PRELIMINARYCY14B108L, CY14B108N AutoStore Operation Device OperationSRAM Read SRAM WritePRELIMINARY Hardware RECALL Power UpSoftware STORE Software RECALLTable 2. Mode Selection PowerPRELIMINARY CY14B108L, CY14B108NBest Practices Preventing AutoStoreData Protection Noise ConsiderationsPRELIMINARY DC Electrical CharacteristicsMaximum Ratings Operating RangeAC Test Conditions Data Retention and EnduranceCapacitance Thermal ResistanceCY14B108L, CY14B108N AC Switching CharacteristicsSwitching Waveforms PRELIMINARYFigure 7. SRAM Write Cycle #1 WE Controlled3, 14, 15 PRELIMINARYCY14B108L, CY14B108N Figure 6. SRAM Read Cycle #2 CE and OE Controlled3, 11Controlled3, 14, 15 PRELIMINARYCY14B108L, CY14B108N + FeedbackCY14B108L, CY14B108N AutoStore/Power Up RECALLSwitching Waveforms PRELIMINARYCY14B108L, CY14B108N Software Controlled STORE/RECALL CycleSwitching Waveforms PRELIMINARYCY14B108L, CY14B108N Hardware STORE CycleSwitching Waveforms PRELIMINARYPRELIMINARY For x8 ConfigurationFor x16 Configuration Truth Table For SRAM OperationsCY14B108L, CY14B108N Ordering InformationPRELIMINARY CY14B108L, CY14B108N Ordering Information continuedPRELIMINARY CY 14 B 108L-ZS P 20 X C T Part Numbering NomenclaturePRELIMINARY CY14B108L, CY14B108NFigure 15. 44-Pin TSOP II Package DiagramsPRELIMINARY CY14B108L, CY14B108NFigure 16. 48-Ball FBGA - 6 mm x 10 mm x 1.2 mm Package Diagrams continuedPRELIMINARY CY14B108L, CY14B108NFigure 17. 54-Pin TSOP II Package Diagrams continuedPRELIMINARY CY14B108L, CY14B108NDocument Title CY14B108L/CY14B108N 8 Mbit 1024K x 8/512K x 16 nvSRAM Document History PagePRELIMINARY CY14B108L, CY14B108NProducts Sales, Solutions, and Legal InformationPSoC Solutions Worldwide Sales and Design Support