Cypress manual Preliminary, CY14B108L, CY14B108N, Pin Definitions

					PRELIMINARY					CY14B108L, CY14B108N
Table 1. Pin Definitions
Pin Name			I/O Type				Description
A0 – A19			Input	Address Inputs Used to Select one of the 1,048,576 bytes of the nvSRAM for x8 Configuration.
A0 – A18				Address Inputs Used to Select one of the 524,288 words of the nvSRAM for x16 Configuration.
DQ0 – DQ7			Input/Output	Bidirectional Data IO Lines for x8 Configuration. Used as input or output lines depending on
				operation.
DQ0 – DQ15				Bidirectional Data IO Lines for x16 Configuration. Used as input or output lines depending on
				operation.
			Input	Write Enable Input, Active LOW. When selected LOW, data on the IO pins is written to the specific
		WE
				address location.
			Input	Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
		CE
			Input	Output Enable, Active LOW. The active LOW					input enables the data output buffers during read
								OE
		OE
				cycles. IO pins are tri-stated on deasserting OE HIGH.
			Input	Byte High Enable, Active LOW. Controls DQ15 - DQ8.
	BHE
			Input	Byte Low Enable, Active LOW. Controls DQ7 - DQ0.
	BLE
	VSS		Ground	Ground for the Device. Must be connected to the ground of the system.
	VCC		Power Supply	Power Supply Inputs to the Device.
			Input/Output	Hardware STORE Busy			. When LOW this output indicates that a Hardware STORE is in
						(HSB)
	HSB
				progress. When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak
				internal pull up resistor keeps this pin HIGH if not connected (connection optional). After each STORE
				operation HSB will be driven HIGH for short time with standard output high current.
VCAP			Power Supply	AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
				nonvolatile elements.
		NC	No Connect	No Connect. This pin is not connected to the die.

Document #: 001-45523 Rev. *B Page 3 of 24

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