Contents
Logic Block Diagram1
Features
PRELIMINARY
CY14B108L, CY14B108N
12 Top View 13 not to scale
Pinouts
Top View
not to scale
Table 1. Pin Definitions
PRELIMINARY
CY14B108L, CY14B108N
SRAM Read
Device Operation
SRAM Write
AutoStore Operation
Software STORE
Hardware RECALL Power Up
Software RECALL
PRELIMINARY
PRELIMINARY
Power
CY14B108L, CY14B108N
Table 2. Mode Selection
Data Protection
Preventing AutoStore
Noise Considerations
Best Practices
Maximum Ratings
DC Electrical Characteristics
Operating Range
PRELIMINARY
Capacitance
Data Retention and Endurance
Thermal Resistance
AC Test Conditions
Switching Waveforms
AC Switching Characteristics
PRELIMINARY
CY14B108L, CY14B108N
CY14B108L, CY14B108N
PRELIMINARY
Figure 6. SRAM Read Cycle #2 CE and OE Controlled3, 11
Figure 7. SRAM Write Cycle #1 WE Controlled3, 14, 15
CY14B108L, CY14B108N
PRELIMINARY
+ Feedback
Controlled3, 14, 15
Switching Waveforms
AutoStore/Power Up RECALL
PRELIMINARY
CY14B108L, CY14B108N
Switching Waveforms
Software Controlled STORE/RECALL Cycle
PRELIMINARY
CY14B108L, CY14B108N
Switching Waveforms
Hardware STORE Cycle
PRELIMINARY
CY14B108L, CY14B108N
For x16 Configuration
For x8 Configuration
Truth Table For SRAM Operations
PRELIMINARY
CY14B108L, CY14B108N
Ordering Information
PRELIMINARY
CY14B108L, CY14B108N
Ordering Information continued
PRELIMINARY
PRELIMINARY
Part Numbering Nomenclature
CY14B108L, CY14B108N
CY 14 B 108L-ZS P 20 X C T
PRELIMINARY
Package Diagrams
CY14B108L, CY14B108N
Figure 15. 44-Pin TSOP II
PRELIMINARY
Package Diagrams continued
CY14B108L, CY14B108N
Figure 16. 48-Ball FBGA - 6 mm x 10 mm x 1.2 mm
PRELIMINARY
Package Diagrams continued
CY14B108L, CY14B108N
Figure 17. 54-Pin TSOP II
PRELIMINARY
Document History Page
CY14B108L, CY14B108N
Document Title CY14B108L/CY14B108N 8 Mbit 1024K x 8/512K x 16 nvSRAM
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